Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 )

Change subject: soc/intel/common/cpu: Update COS mask calculation for nem enhanced mode
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Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 
PS3, Line 20: 
            : Also the COS mask selection is mapped to bit 32:33 of MSR
            : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before
            : MSR write instead of eax(mas 31:0). This implementation corrects that
            : as well.
> does this mean that the enhanced mode never worked correctly in the first place? IOW, we were writin […]

I am checking on this, on the SKL, CNL, ICL it still maps to LSB.
In my CML testing I am seeing a hang with this implementation. Need to confirm on the offset mapping.

https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

PS3:
> Ok, I see. […]

yes, we configure the mask2 with the RW data mapped ways configured for eviction and start filling in the cache lines i.e access one DWORD from each cache line of the dataStack region to map all dataStack into the cache. and then toggle the mask to protect the data from eviction so that the RW data does not get evicted out.