Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/#/c/19557/8/src/soc/rockchip/rk3399/clock.c File src/soc/rockchip/rk3399/clock.c:
Line 361: * hang in assert() with reboot tests.
Which assert() is failing in the failure case? The one below? (That wouldn'
Yes, it's related to "assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);"
As the previous said:"
+ if (!(dpll_cfg->refdiv && dpll_cfg->refdiv <=6)) { + printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n",__func__, + dpll_cfg->refdiv); + return; + } That's fine from the short test. I don't see the error log.
That's weird, we should printf the log if the assert() failed."
e.g: assert(0) should output the error log.
PS8, Line 414: Assert
This should actually read "Deassert reset", right?
oh, right.
Line 423: divval << PLL_SSMOD_DIVVAL_SHIFT));
You're already writing divval above, why write it again?
Okay. drop it.