[S] Change in coreboot[master]: ec/google/chromec: Host event support of DTTS

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67793 )

Change subject: ec/google/chromec: Host event support of DTTS
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Patch Set 11:

(1 comment)

File src/ec/google/chromeec/acpi/ec.asl:

https://review.coreboot.org/c/coreboot/+/67793/comment/5e77e1dc_4b2d9e40 
PS11, Line 20: #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
Do we really need this conditional check? Same for all the places that we introduced.

Reason: This ASL code that applies to all SoCs has SoC specific check. Also DPTC method is accessed only if it is present. Hence the question.