[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli.

Hello Angel Pons, Subrata Banik, Tarun Tuli, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76687?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)

Change subject: soc/intel/alderlake: Disable PCIe clock gating
......................................................................

soc/intel/alderlake: Disable PCIe clock gating

Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal
connected. The CLK_REQ is used to wake the silicon when link entered
L1 link-state. L1 link-state is also entered on PCI-PM D3, even with
ASPM L1 disabled. When no CLK_REQ signal is used, for example when
it's using a free running clock the silicon will never wake from L1
link state. This will trigger a MCE.

Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work
around this issue by disabling ClockGating. Disabling ClockGating
should be avoided as the silicon draws more power when it is idle.

TEST: Verified on two boards, one with missing CLK_REQ on a PCH
      root port, that the code does the right decision to disable
      UPD PchPcieClockGating when necessary.

Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/76687/2