Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

[Subrata Banik (Code Review)]

Attention is currently required from: Kevin Chang, Kane Chen, Paul Menzel, Tim Wawrzynczak.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 )

Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................

Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/62919/comment/df6f1bef_195438f5 
PS2, Line 635: s_cfg->PcieRpAspm[i] = config->pcierpaspm[i];
> by doing this, all projects without devicetree settings , PcieRpAspm will be 0.
>
> also , i don't understand why you need to control aspm on root port side.
> have you checked ASPM is working in OS?
> you should compare lspci -vvv on pcie device and root port

I agree with Kane