Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 48ad36e..933de8f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -19,7 +19,11 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + +/* PCH M.2 SSD */ +PAD_CFG_GPO(GPP_B16, 1, PLTRST), +PAD_CFG_GPO(GPP_H0 , 1, PLTRST), + };
/* Early pad configuration in bootblock */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38286/1/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/38286/1/src/mainboard/intel/tglrvp/... PS1, Line 25: PAD_CFG_GPO(GPP_H0 , 1, PLTRST), space prohibited before that ',' (ctx:WxW)
Wonkyu Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38286/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/38286/2/src/mainboard/intel/tglrvp/... PS2, Line 24: PAD_CFG_GPO(GPP_H0 , 1, PLTRST), space prohibited before that ',' (ctx:WxW)
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38286
to look at the new patch set (#3).
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38286
to look at the new patch set (#4).
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 22: /* PCH M.2 SSD */ care to give a tab to start?
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 23: remove white space?
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 24: remove white space?
Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, caveh jalali, Shaunak Saha, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38286
to look at the new patch set (#5).
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 22: /* PCH M.2 SSD */
care to give a tab to start?
Ack
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 23:
remove white space?
This is one space, we should have after ,
https://review.coreboot.org/c/coreboot/+/38286/4/src/mainboard/intel/tglrvp/... PS4, Line 24:
remove white space?
this is 2 spaces. Remove 1 spaces.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 5: Code-Review+1
Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, caveh jalali, build bot (Jenkins), Shaunak Saha,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38286
to look at the new patch set (#6).
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38286/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
Patch Set 6: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38286 )
Change subject: mb/tglrvp: update gpio pin mux for NVMe ......................................................................
mb/tglrvp: update gpio pin mux for NVMe
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 48ad36e..afe73c8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -19,7 +19,9 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* PCH M.2 SSD */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + PAD_CFG_GPO(GPP_H0, 1, PLTRST), };
/* Early pad configuration in bootblock */
-
build bot (Jenkins) (Code Review) -
Subrata Banik (Code Review)
-
Wonkyu Kim (Code Review)