Attention is currently required from: Xixi Chen, Yidi Lin, Yu-Ping Wu.
Paul Menzel has posted comments on this change by Xixi Chen. ( https://review.coreboot.org/c/blobs/+/83748?usp=email )
Change subject: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1 ......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/blobs/+/83748/comment/64cfb84f_b72e3205?usp=em... : PS5, Line 9: readed read
https://review.coreboot.org/c/blobs/+/83748/comment/7d7700d6_45f57d47?usp=em... : PS5, Line 12: let make?
https://review.coreboot.org/c/blobs/+/83748/comment/4cb390e6_e4781fac?usp=em... : PS5, Line 12: value(from full-k reference) Please add a space before (.
https://review.coreboot.org/c/blobs/+/83748/comment/54b05dbf_57c0cd9b?usp=em... : PS5, Line 9: For fast-k RX flow, Vref value is readed from the MRC_CACHE, but the : preferred RX Vref value 0xE is set, with no re-calibration. But some : DRAM vendor may use higher RX Vref value, increase the default RX : Vref value(from full-k reference) to let different DRAM RX Vref : compatible. : Please make use of 72 characters per line.
https://review.coreboot.org/c/blobs/+/83748/comment/d2fe5fb8_2d1142c3?usp=em... : PS5, Line 16: TEST=Check the fast-k RX Vref value is normal How? What DRAM vendor/model?