[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.

Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )

Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
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Patch Set 123:

(7 comments)

File src/soc/intel/common/block/acpi/acpi/northbridge.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/1f01ead4_301804e7?usp... :
PS104, Line 284: 	Name (_UID, 1)
> move this ASL to new CL: […]

Acknowledged

File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/fbe5d2fb_40d45bae?usp... :
PS104, Line 3: #define R_ICLK_PCR_CAMERA1	0x8000
             : #define B_ICLK_PCR_FREQUENCY	0x1
             : #define B_ICLK_PCR_REQUEST	0x2
             :
> I add TASK 16 for TODO itme in https://partnerissuetracker.corp.google. […]

Acknowledged

File src/soc/intel/pantherlake/acpi/southbridge.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/6602a70e_23d59723?usp... :
PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
> Subrata, I don't quite follow. The CL 84138 you mentioned contains changes removing soc/itss.h. I don't see any change for related marco guarding.

if SOC_INTEL_COMMON_BLOCK_IOE_P2SB is default set to true for PTL SOC then what is the point of keeping `#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)` while adding `#include <soc/intel/common/acpi/ioe_pcr.asl>`? isn't the case is always true when PTL SOC selects SOC_INTEL_COMMON_BLOCK_IOE_P2SB unconditionally. Therefore, asked to remove this guarding

File src/soc/intel/pantherlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/db993258_466278c2?usp... :
PS123, Line 216: 		Sleep (100)
why we need static delay, this will impact the sleep_resume time KPI which is 500ms.

Please file a bug to continue to have discussion. I don't think we need to issue static delay. At kernel space the delays should be like inherited delays.

https://review.coreboot.org/c/coreboot/+/83772/comment/41ee22b4_c49e1656?usp... :
PS123, Line 218: 		If (CondRefOf (_SB.PCI0.TXHC)) {
               : 			/* Invoke PCIe root ports wake event handler */
               : 			_SB.PCI0.TRP0.HPEV()
               : 		}
               : 		/* Check Root Port 0 for a Hot Plug Event if the port is enabled */
               : 		If (((_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && _SB.PCI0.TRP0.HPSX)) {
               : 			If (_SB.PCI0.TRP0.PDCX) {
               : 				/* Clear all status bits */
               : 				_SB.PCI0.TRP0.PDCX = 1
               : 				_SB.PCI0.TRP0.HPSX = 1
               : 				/*
               : 				 * Intercept Presence Detect Changed interrupt and make sure
               : 				 * the L0s is disabled on empty slots.
               : 				 */
               : 				If (!_SB.PCI0.TRP0.PDSX) {
               : 					/*
               : 					 * The PCIe slot is empty, so disable L0s on hot unplug.
               : 					 */
               : 					_SB.PCI0.TRP0.L0SE = 0
               : 				}
               : 				/* Performs proper notification to the OS. */
               : 				Notify (_SB.PCI0.TRP0, 0)
               : 			} Else {
               : 				/* False event. Clear Hot-Plug status, then exit. */
               : 				_SB.PCI0.TRP0.HPSX = 1
               : 			}
               : 		}
please create helper function and call into w/o adding implementation for each RP here.

File src/soc/intel/pantherlake/acpi/tcss_dma.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/7b9e46cc_b7d8e602?usp... :
PS104, Line 22: 	Offset (0xFF),
              : 	DMAD, 8         /* 31:24 DMA Active Delay */
> I add TASK 17 for TODO item in https://partnerissuetracker.corp.google. […]

Acknowledged

File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/c4e04463_23022f87?usp... :
PS123, Line 236: 	}
please leave one space before