[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................

Patch Set 65:

(10 comments)

File src/soc/intel/pantherlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/83635/comment/52d38cca_5105b7f1?usp... :
PS64, Line 6: 9
is this a 9W silicon ?

what is the source behind this configuration ?

https://review.coreboot.org/c/coreboot/+/83635/comment/5a575b1f_7626f28b?usp... :
PS64, Line 13: 100
why 100 ?

https://review.coreboot.org/c/coreboot/+/83635/comment/f9211982_454770f8?usp... :
PS64, Line 17: off
`on` may be ?

https://review.coreboot.org/c/coreboot/+/83635/comment/805756cb_6155d261?usp... :
PS64, Line 48: 		device pci 08.0 alias gna off end
i don't see this device listed inside PTL EDS 815002

https://review.coreboot.org/c/coreboot/+/83635/comment/d7361308_cd4fe07b?usp... :
PS64, Line 49: off
want to keep crashlog `on` ?

https://review.coreboot.org/c/coreboot/+/83635/comment/5fd5aef8_35c5dcf7?usp... :
PS64, Line 65: 				end
Please add

```
        chip drivers/usb/acpi
         device usb 3.3 alias tcss_usb3_port3 off end
        end
```

File src/soc/intel/pantherlake/p2sb.c:

https://review.coreboot.org/c/coreboot/+/83635/comment/514c9b04_a879c8eb?usp... :
PS64, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
please add this file as part of the ramstage CL as there is no consumer of p2sb.c in romstage

File src/soc/intel/pantherlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/83635/comment/ac4dcbd3_b8e96902?usp... :
PS64, Line 36: 		timestamp_add_now(TS_CSE_FW_SYNC_START);
we have added these timestamp inside `cse_fw_sync` hence, please drop

```
void cse_fw_sync(void)
{
    if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
    	return;

timestamp_add_now(TS_CSE_FW_SYNC_START);
    do_cse_fw_sync();
    timestamp_add_now(TS_CSE_FW_SYNC_END);
}

```

https://review.coreboot.org/c/coreboot/+/83635/comment/29382d7c_401c12cc?usp... :
PS64, Line 37: 		cse_fw_sync();
why are you enforcing CSE sync in romstage ?

Please follow romstage.c from MTL

```
    if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
    	cse_fill_bp_info();
    	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
    		cse_fw_sync();
    }
```

https://review.coreboot.org/c/coreboot/+/83635/comment/05cbb879_6034d7f0?usp... :
PS64, Line 40: 
missing 
```
    /* Update coreboot timestamp table with CSE timestamps */
    if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
    	cse_get_telemetry_data();
```