Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43191 )
Change subject: soc/intel/baytrail/elog.c: Align with Braswell ......................................................................
soc/intel/baytrail/elog.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/baytrail/elog.c 1 file changed, 20 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43191/1
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 93a43c5..75c080d 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <stdint.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <stdint.h>
static void log_power_and_resets(const struct chipset_power_state *ps) { @@ -17,36 +17,30 @@ elog_add_event(ELOG_TYPE_PWROK_FAIL); }
- if (ps->gen_pmcon1 & SUS_PWR_FLR) { + if (ps->gen_pmcon1 & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - }
- if (ps->gen_pmcon1 & RPS) { + if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - }
- if (ps->tco_sts & SECOND_TO_STS) { + if (ps->tco_sts & SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); - }
- if (ps->pm1_sts & PRBTNOR_STS) { + if (ps->pm1_sts & PRBTNOR_STS) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - }
- if (ps->gen_pmcon1 & SRS) { + if (ps->gen_pmcon1 & SRS) elog_add_event(ELOG_TYPE_RESET_BUTTON); - }
- if (ps->gen_pmcon1 & GEN_RST_STS) { + if (ps->gen_pmcon1 & GEN_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); - } }
static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | - PCIE_WAKE2_STS | PCIE_WAKE1_STS | - PCIE_WAKE0_STS; + const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | + PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; + uint32_t gpe0_sts; uint32_t gpio_mask; int i; @@ -54,33 +48,27 @@ /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
- if (ps->pm1_sts & WAK_STS) { + if (ps->pm1_sts & WAK_STS) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - } + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
- if (ps->pm1_sts & PWRBTN_STS) { + if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - }
- if (ps->pm1_sts & RTC_STS) { + if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - }
- if (gpe0_sts & PME_B0_EN) { + if (gpe0_sts & PME_B0_EN) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - }
- if (gpe0_sts & pcie_wake_mask) { + if (gpe0_sts & pcie_wake_mask) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - }
gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { - if (gpio_mask & gpe0_sts) { + if (gpio_mask & gpe0_sts) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } gpio_mask <<= 1; i++; } @@ -91,8 +79,8 @@ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps == NULL) { - printk(BIOS_DEBUG, "Not logging power state information. " - "Power state not found in cbmem.\n"); + printk(BIOS_DEBUG, + "Not logging power state information. Power state not found in cbmem.\n"); return; }
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43191 )
Change subject: soc/intel/baytrail/elog.c: Align with Braswell ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43191 )
Change subject: soc/intel/baytrail/elog.c: Align with Braswell ......................................................................
soc/intel/baytrail/elog.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/elog.c 1 file changed, 20 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 93a43c5..75c080d 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> -#include <stdint.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <stdint.h>
static void log_power_and_resets(const struct chipset_power_state *ps) { @@ -17,36 +17,30 @@ elog_add_event(ELOG_TYPE_PWROK_FAIL); }
- if (ps->gen_pmcon1 & SUS_PWR_FLR) { + if (ps->gen_pmcon1 & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - }
- if (ps->gen_pmcon1 & RPS) { + if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - }
- if (ps->tco_sts & SECOND_TO_STS) { + if (ps->tco_sts & SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); - }
- if (ps->pm1_sts & PRBTNOR_STS) { + if (ps->pm1_sts & PRBTNOR_STS) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - }
- if (ps->gen_pmcon1 & SRS) { + if (ps->gen_pmcon1 & SRS) elog_add_event(ELOG_TYPE_RESET_BUTTON); - }
- if (ps->gen_pmcon1 & GEN_RST_STS) { + if (ps->gen_pmcon1 & GEN_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); - } }
static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | - PCIE_WAKE2_STS | PCIE_WAKE1_STS | - PCIE_WAKE0_STS; + const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | + PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; + uint32_t gpe0_sts; uint32_t gpio_mask; int i; @@ -54,33 +48,27 @@ /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
- if (ps->pm1_sts & WAK_STS) { + if (ps->pm1_sts & WAK_STS) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - } + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
- if (ps->pm1_sts & PWRBTN_STS) { + if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - }
- if (ps->pm1_sts & RTC_STS) { + if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - }
- if (gpe0_sts & PME_B0_EN) { + if (gpe0_sts & PME_B0_EN) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - }
- if (gpe0_sts & pcie_wake_mask) { + if (gpe0_sts & pcie_wake_mask) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - }
gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { - if (gpio_mask & gpe0_sts) { + if (gpio_mask & gpe0_sts) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } gpio_mask <<= 1; i++; } @@ -91,8 +79,8 @@ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps == NULL) { - printk(BIOS_DEBUG, "Not logging power state information. " - "Power state not found in cbmem.\n"); + printk(BIOS_DEBUG, + "Not logging power state information. Power state not found in cbmem.\n"); return; }
-
Angel Pons (Code Review) -
Tim Wawrzynczak (Code Review)