Change in coreboot[master]: soc/mediatek/mt8192: Save dramc shuffle result after calibration
Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44714
to review the following change.
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/1
diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index ce24829..67e2340 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -111,3 +111,85 @@ *(cali->pll_mode) = pll_mode; }
+void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("wait dramc to shuffle sram done, tmp:%d.\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); +} + +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE)<< 1); + dramc_dbg("wait shuffle sram to dramc done.\n"); + } while (tmp != 0x3); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 5ca7bce..3273f28 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -290,6 +290,11 @@ get_dram_info_after_cal(&cali);
dramc_ac_timing_optimize(&cali); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); + + /* for frequency switch in dramc_mode_reg_init phase */ + if (first_freq_k) + dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1);
first_freq_k= false; }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44714/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_dvfs.c:
https://review.coreboot.org/c/coreboot/+/44714/1/src/soc/mediatek/mt8192/dra... PS1, Line 185: MISC_DMA_DEBUG0_APB_DONE)<< 1); need consistent spacing around '<<' (ctx:VxW)
Hello build bot (Jenkins), Julius Werner, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44714
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/2
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 87 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/36
Yidi Lin has uploaded a new patch set (#41) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/41
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
Patch Set 41:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_dvfs.c:
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 135: MISC_DMA_DEBUG0_APB_DONE Align with &ch[chn]
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 136: wait dramc to shuffle sram done, tmp:%d. Waiting dramc to shuffle sram, tmp: %u
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 180: wait shuffle sram to dramc done. Waiting shuffle sram to dramc, tmp: %u
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 182: Indentation
Yidi Lin has uploaded a new patch set (#44) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/44
Xi Chen has uploaded a new patch set (#49) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 89 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44714/49
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
Patch Set 48:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_dvfs.c:
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 135: MISC_DMA_DEBUG0_APB_DONE
Align with &ch[chn]
Ack
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 136: wait dramc to shuffle sram done, tmp:%d.
Waiting dramc to shuffle sram, tmp: %u
Ack
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 180: wait shuffle sram to dramc done.
Waiting shuffle sram to dramc, tmp: %u
Ack
https://review.coreboot.org/c/coreboot/+/44714/41/src/soc/mediatek/mt8192/dr... PS41, Line 182:
Indentation
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
Patch Set 49: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44714 )
Change subject: soc/mediatek/mt8192: Save dramc shuffle result after calibration ......................................................................
soc/mediatek/mt8192: Save dramc shuffle result after calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44714 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 89 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index c784dfb..7fc8d28 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -104,3 +104,87 @@ pll_mode = !pll_mode; *(cali->pll_mode) = pll_mode; } + +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("Waiting dramc to shuffle sram, tmp: %u\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); +} + +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("Waiting shuffle sram to dramc, tmp: %u\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 0373c82..b4e6e1a 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -321,6 +321,11 @@ get_dram_info_after_cal(&cali);
dramc_ac_timing_optimize(&cali); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); + + /* for frequency switch in dramc_mode_reg_init phase */ + if (first_freq_k) + dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1);
first_freq_k = false; }
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build bot (Jenkins) (Code Review) -
CK HU (Code Review)
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Hung-Te Lin (Code Review)
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Xi Chen (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)