[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allow Memory POR independent of RMT

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84741?usp=email )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp: Allow Memory POR independent of RMT
......................................................................

soc/intel/xeon_sp: Allow Memory POR independent of RMT

TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.

Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 3 insertions(+), 4 deletions(-)

Approvals:
  Shuo Liu: Looks good to me, approved
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index b84a8ff..6fad812 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -174,10 +174,9 @@
      Enable Rank Margining Tool. This option is intended for debugging and
      validation and should normally be disabled.

-config RMT_MEM_POR_FREQ
+config MEM_POR_FREQ
    bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage"
    default n
-	depends on ENABLE_RMT
    help
      When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR)
      restriction on DDR5 frequency & voltage settings.
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index b05c7e7..4d95a33 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -241,9 +241,9 @@
    	mupd->FspmConfig.serialDebugMsgLvl = 0x3;
    	mupd->FspmConfig.AllowedSocketsInParallel = 0x1;
    	mupd->FspmConfig.EnforcePopulationPor = 0x1;
-		if (CONFIG(RMT_MEM_POR_FREQ))
-			mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
    }
+	if (CONFIG(MEM_POR_FREQ))
+		mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;

/* SPR-FSP has no UPD to disable HDA, so do it manually here... */
    if (!is_devfn_enabled(PCH_DEVFN_HDA))