Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31433
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have change the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so delacre that in common code.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31433/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..0030961 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2969,6 +2969,7 @@ #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 #define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12 0x3185 +#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1 0x3EA1 #define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1 0x3EA0 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7..8eebd12 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, PCI_DEVICE_ID_INTEL_GLK_IGD, PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG@9 PS1, Line 9: have change changed
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG@10 PS1, Line 10: delacre declare
Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31433
to look at the new patch set (#2).
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31433/2
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG@9 PS1, Line 9: have change
changed
Done
https://review.coreboot.org/#/c/31433/1//COMMIT_MSG@10 PS1, Line 10: delacre
declare
Done
Hello Patrick Rudolph, Lean Sheng Tan, Paul Menzel, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31433
to look at the new patch set (#3).
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID had been changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 5 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31433/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 3: Code-Review+1
We can boot with v0 stepping CPU successfully.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/31433/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31433/3//COMMIT_MSG@11 PS3, Line 11: had been was
Hello Patrick Rudolph, EricR Lai, Lean Sheng Tan, Paul Menzel, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31433
to look at the new patch set (#4).
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 5 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/31433/4
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31433/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31433/3//COMMIT_MSG@11 PS3, Line 11: had been
was
Done
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
Patch Set 4: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31433 )
Change subject: soc/intel/common: Add whiskeylake celeron v-0 support ......................................................................
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Reviewed-on: https://review.coreboot.org/c/31433 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 5 files changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved EricR Lai: Looks good to me, but someone else must approve
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0..0030961 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2969,6 +2969,7 @@ #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 #define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12 0x3185 +#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1 0x3EA1 #define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1 0x3EA0 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 8839816..e61c7f4 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -37,6 +37,7 @@ { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, + { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0"}, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"}, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 5f5c8cf..7deaaa8 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,6 +70,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7..8eebd12 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, PCI_DEVICE_ID_INTEL_GLK_IGD, PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index b0fd857..fca6ca5 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea
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Duncan Laurie (Code Review) -
EricR Lai (Code Review)
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Lijian Zhao (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)