Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL

[V Sowmya (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63372 )


Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
......................................................................

soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL

This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU
specific value of 108.

Signed-off-by: V Sowmya <[e-mail]>
Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63372/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd2c0be..ca464b6 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -42,6 +42,7 @@
 #define ICC_MAX_TDP_45W		34250
 #define ICC_MAX_TDP_15W_28W	32000
 #define ICC_MAX_ID_ADL_M_MA	12000
+#define ICC_MAX_ID_ADL_N_MA	27000
 
 /*
  * ME End of Post configuration
@@ -346,6 +347,11 @@
 	case PCI_DID_INTEL_ADL_M_ID_1:
 	case PCI_DID_INTEL_ADL_M_ID_2:
 		return ICC_MAX_ID_ADL_M_MA;
+	case PCI_DID_INTEL_ADL_N_ID_1:
+	case PCI_DID_INTEL_ADL_N_ID_2:
+	case PCI_DID_INTEL_ADL_N_ID_3:
+	case PCI_DID_INTEL_ADL_N_ID_4:
+		return ICC_MAX_ID_ADL_N_MA;
 	default:
 		printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",
 			mch_id);

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715
Gerrit-Change-Number: 63372
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <[e-mail]>
Gerrit-Reviewer: Tim Wawrzynczak <[e-mail]>
Gerrit-Attention: Tim Wawrzynczak <[e-mail]>
Gerrit-MessageType: newchange