Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )

Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
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Patch Set 64:

(4 comments)

https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... 
File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... 
PS64, Line 23: register "PcieRpEnable[1]" = "1"
             : 	register "PcieRpEnable[5]" = "1"
             : 	register "PcieRpEnable[8]" = "1"
             : 	register "PcieRpEnable[20]" = "1"
             : 	register "PcieRpEnable[21]" = "1"
These should be moved into the corresponding PCIe root port devices, alongside the clkreq and clksrc settings:

device pci 1c.1 on	# Aspeed Graphics
    register "PcieRpEnable[1]" = "1"
    register "PcieClkSrcUsage[1]" = "0x80"
    register "PcieClkSrcClkReq[1]" = "1"
 end

https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... 
PS64, Line 29: 	register "PcieClkSrcUsage[0]" = "0x80"
             : 	register "PcieClkSrcUsage[1]" = "0x80"
             : 	register "PcieClkSrcUsage[2]" = "0x80"
             : 	register "PcieClkSrcUsage[3]" = "0x80"
             : 	register "PcieClkSrcUsage[4]" = "0x80"
             : 	register "PcieClkSrcUsage[5]" = "0x80"
             : 	register "PcieClkSrcUsage[6]" = "0x80"
             : 	register "PcieClkSrcUsage[7]" = "0x80"
             : 	register "PcieClkSrcUsage[8]" = "0x80"
             : 	register "PcieClkSrcUsage[9]" = "0x80"
             : 	register "PcieClkSrcUsage[10]" = "0x80"
             : 	register "PcieClkSrcUsage[11]" = "0x80"
             : 	register "PcieClkSrcUsage[12]" = "0x80"
             : 	register "PcieClkSrcUsage[13]" = "0x80"
             : 	register "PcieClkSrcUsage[14]" = "0x80"
             : 	register "PcieClkSrcUsage[15]" = "0x80"
             : 
             : 	register "PcieClkSrcClkReq[0]" = "0"
             : 	register "PcieClkSrcClkReq[1]" = "1"
             : 	register "PcieClkSrcClkReq[2]" = "2"
             : 	register "PcieClkSrcClkReq[3]" = "3"
             : 	register "PcieClkSrcClkReq[4]" = "4"
             : 	register "PcieClkSrcClkReq[5]" = "5"
             : 	register "PcieClkSrcClkReq[6]" = "6"
             : 	register "PcieClkSrcClkReq[7]" = "7"
             : 	register "PcieClkSrcClkReq[8]" = "8"
             : 	register "PcieClkSrcClkReq[9]" = "9"
             : 	register "PcieClkSrcClkReq[10]" = "10"
             : 	register "PcieClkSrcClkReq[11]" = "11"
             : 	register "PcieClkSrcClkReq[12]" = "12"
             : 	register "PcieClkSrcClkReq[13]" = "13"
             : 	register "PcieClkSrcClkReq[14]" = "14"
             : 	register "PcieClkSrcClkReq[15]" = "15"
Drop clksrc and clkreq for unused ports, shouldn't be needed.

https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... 
PS64, Line 104: register "HeciEnabled" = "1"
Put this inside the ME Interface 1 device in devicetree

https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... 
PS64, Line 109: register "InternalGfx" = "1"
Put this inside the iGPU device in the devicetree