Change in coreboot[master]: soc/intel/common/block: Update LPC lib

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/21605

Change subject: soc/intel/common/block: Update LPC lib
......................................................................

soc/intel/common/block: Update LPC lib

Add wrapper functions to support SoC specific functionality:
 1. Setup PCH LPC interrupt routing.
 2. Get SoC's generic IO decoder configuration settings.

Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi 
---
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/lpc/lpc_lib.c
2 files changed, 69 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21605/1

diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 596c2b5..455f6c2 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -38,6 +38,14 @@
 #define  LPC_IOE_COMB_EN                (1 << 1)
 #define  LPC_IOE_COMA_EN                (1 << 0)

+#define PCR_DMI_LPCLGIR1        0x2730
+#define PCR_DMI_LPCLGIR2        0x2734
+#define PCR_DMI_LPCLGIR3        0x2738
+#define PCR_DMI_LPCLGIR4        0x273c
+
+#define PCR_DMI_LPCIOD          0x2770
+#define PCR_DMI_LPCIOE          0x2774
+
 /* Serial IRQ control. SERIRQ_QUIET is the default (0). */
 enum serirq_mode {
    SERIRQ_QUIET,
@@ -75,6 +83,8 @@
 void lpc_set_eiss(void);
 /* Set LPC Serial IRQ mode. */
 void lpc_set_serirq_mode(enum serirq_mode mode);
+/* Enable CLKRUN_EN for power gating LPC. */
+void lpc_enable_pci_clk_cntl(void);
 /*
 * Setup I/O Decode Range Register for LPC
 * ComA Range 3F8h-3FFh [2:0]
@@ -82,5 +92,13 @@
 * Enable ComA and ComB Port
 */
 void lpc_io_setup_comm_a_b(void);
+/* Enable PCH LPC by setting up generic decode range registers. */
+void pch_enable_lpc(void);
+/* Setup PCH LPC interrupt routing. */
+void pch_lpc_interrupt_init(void);
+/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */
+void soc_pch_pirq_init(const struct device *dev);
+/* Get SoC's generic IO decoder configuration settings. */
+void soc_get_gen_io_dec_config(const struct device *dev, uint32_t *gen_io_dec);

#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 6b5f29a..6d695ee 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -18,12 +18,16 @@
 #define __SIMPLE_DEVICE__

#include <assert.h>
+#include <chip.h>
 #include <console/console.h>
 #include <device/pci.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
 #include <lib.h>
 #include "lpc_def.h"
 #include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>

void lpc_enable_fixed_io_ranges(uint16_t io_enables)
 {
@@ -235,3 +239,50 @@
    /* Enable ComA and ComB Port */
    lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN);
 }
+
+void pch_enable_lpc(void)
+{
+	/* Lookup device tree in romstage */
+	const struct device *dev;
+	uint32_t gen_io_dec[4];
+
+	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	if (!dev || !dev->chip_info)
+		return;
+
+	soc_get_gen_io_dec_config(dev, gen_io_dec);
+
+	/* Set in PCI generic decode range registers */
+	pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(0),
+		gen_io_dec[0]);
+	pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(1),
+		gen_io_dec[1]);
+	pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(2),
+		gen_io_dec[2]);
+	pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(3),
+		gen_io_dec[3]);
+
+	/* Mirror these same settings in DMI PCR */
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
+}
+
+void pch_lpc_interrupt_init(void)
+{
+	const struct device *dev;
+
+	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	if (!dev || !dev->chip_info)
+		return;
+
+	soc_pch_pirq_init(dev);
+}
+
+void lpc_enable_pci_clk_cntl(void)
+{
+	device_t dev = PCH_DEV_LPC;
+
+	pci_write_config8(dev, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
+}