Change in coreboot[master]: device/dram/ddr2.c: Be more lax about bit7 for tRR byte in SPD

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21620

Change subject: device/dram/ddr2.c: Be more lax about bit7 for tRR byte in SPD
......................................................................

device/dram/ddr2.c: Be more lax about bit7 for tRR byte in SPD

At least one dimm was found to have an SPD with valid checksum (so
otherwise sane) but without bit7 set.

Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans 
---
M src/device/dram/ddr2.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/21620/1

diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 6f43563..0a6574f 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -188,6 +188,12 @@
  */
 static int spd_decode_tRR_time(u32 *tRR, u8 c)
 {
+	if (!(c & (1 << 7))) {
+		printk(BIOS_DEBUG, "SPD byte12 (tRR) bit7 not set,"
+			" ignoring...");
+		c |= (1 << 7);
+	}
+
    switch (c) {
    default:
    	printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);