Change in coreboot[master]: [WIP] mb/lippert/frontrunner-af: Use common SB800 acpi/fch.asl

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59181 )

Change subject: [WIP] mb/lippert/frontrunner-af: Use common SB800 acpi/fch.asl
......................................................................

[WIP] mb/lippert/frontrunner-af: Use common SB800 acpi/fch.asl

Change-Id: I0516d50b079c8f60312329eef36ca17ea3c94468
Signed-off-by: Kyösti Mälkki 
---
M src/mainboard/lippert/frontrunner-af/dsdt.asl
M src/southbridge/amd/cimx/sb800/acpi/fch.asl
2 files changed, 8 insertions(+), 133 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59181/1

diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index 5f834fc..7a4b652 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -15,8 +15,6 @@

#include <cpu/amd/agesa/family14/acpi/cpu.asl>

-	#include <southbridge/amd/cimx/sb800/acpi/misc_io.asl>
-
    #include "acpi/routing.asl"

/* Contains the supported sleep states for this chipset */
@@ -40,137 +38,8 @@
    		/* Describe the AMD Northbridge */
    		#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>

-			/* Operating System Capabilities Method */
-			Method (_OSC, 4)
-			{
-				/* Check for PCI/PCI-X/PCIe GUID */
-				If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
-				{
-					/* Let OS control everything */
-					Return (Arg3)
-				}
-				Else
-				{
-					/* Unrecognized UUID, so set bit 2 of Arg3 to 1 */
-					CreateDWordField (Arg3, 0, CDW1)
-					CDW1 |= 4
-					Return (Arg3)
-				}
-			} /* End _OSC */
-
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PICM){ Return(APR0) }   /* APIC mode */
-				Return (PR0)                  /* PIC Mode */
-			} /* end _PRT */
-
-
-
-			/* Describe the Southbridge devices */
-
-			#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
-
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			#include <southbridge/amd/cimx/sb800/acpi/usb.asl>
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			#include <southbridge/amd/cimx/sb800/acpi/audio.asl>
-
-			#include <southbridge/amd/cimx/sb800/acpi/lpc.asl>
-
-			/* PCI bridge */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			Name(CRES, ResourceTemplate() {
-				/* Set the Bus number and Secondary Bus number for the PCI0 device
-				 * The Secondary bus range for PCI0 lets the system
-				 * know what bus values are allowed on the downstream
-				 * side of this PCI bus if there is a PCI-PCI bridge.
-				 * PCI buses can have 256 secondary buses which
-				 * range from [0-0xFF] but they do not need to be
-				 * sequential.
-				 */
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,		/* address granularity */
-					0x0000,		/* range minimum */
-					0x00FF,		/* range maximum */
-					0x0000,		/* translation */
-					0x0100,		/* length */
-					,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-				IO(Decode16, 0x004E, 0x004E, 1, 2)	/* SIO config regs */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-				IO(Decode16, 0x0E00, 0x0E00, 1, 0x80)	/* SIO runtime regs */
-#endif
-				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0000,			/* range minimum */
-					0x0CF7,			/* range maximum */
-					0x0000,			/* translation */
-					0x0CF8			/* length */
-				)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0D00,			/* range minimum */
-					0xFFFF,			/* range maximum */
-					0x0000,			/* translation */
-					0xF300			/* length */
-				)
-
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
-				/* memory space for PCI BARs below 4GB */
-				Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-			}) /* End Name(_SB.PCI0.CRES) */
-
-			Method(_CRS, 0) {
-				CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-				CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				MM1B = TOM1
-				Local0 = 0x10000000 << 4
-				Local0 -= TOM1
-				MM1L = Local0
-
-				Return(CRES) /* note to change the Name buffer */
-			} /* end of Method(_SB.PCI0._CRS) */
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>

} /* End Device(PCI0)  */

diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 7cf8bb8..1df2052 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -85,6 +85,12 @@
    	0x0100,		/* length */
    	,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */

+#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) || CONFIG(BOARD_LIPPERT_TOUCAN_AF)
+	IO(Decode16, 0x004E, 0x004E, 1, 2)	/* SIO config regs */
+#endif
+#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
+	IO(Decode16, 0x0E00, 0x0E00, 1, 0x80)	/* SIO runtime regs */
+#endif
    IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)

WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,