Change in coreboot[master]: amd/stoneyridge: Use generic fixed MTRR setup

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23723

Change subject: amd/stoneyridge: Use generic fixed MTRR setup
......................................................................

amd/stoneyridge: Use generic fixed MTRR setup

Add the X86_AMD_FIXED_MTRRS select back to Kconfig.  This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.

Remove the setup from model_15_init.c because this is duplicated
functionality.

BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT

Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/model_15_init.c
2 files changed, 1 insertion(+), 37 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/23723/1

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 8bf577c..de1cb92 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -31,6 +31,7 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
+	select X86_AMD_FIXED_MTRRS
    select ACPI_AMD_HARDWARE_SLEEP_VALUES
    select COLLECT_TIMESTAMPS_NO_TSC
    select DRIVERS_I2C_DESIGNWARE
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index 4bde81e..83fadd0 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -16,7 +16,6 @@
 #include <console/console.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <string.h>
@@ -26,22 +25,9 @@

#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>

-static void msr_rw_dram(unsigned int reg)
-{
-#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM)
-#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \
-		     (RW_DRAM << 8)  | (RW_DRAM))
-
-	msr_t mtrr = rdmsr(reg);
-	mtrr.hi |= ALL_RW_DRAM;
-	mtrr.lo |= ALL_RW_DRAM;
-	wrmsr(reg, mtrr);
-}
-
 static void model_15_init(device_t dev)
 {
    printk(BIOS_DEBUG, "Model 15 Init.\n");
@@ -49,29 +35,6 @@
    int i;
    msr_t msr;

-	disable_cache();
-
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* Send all but A0000-BFFFF to DRAM */
-	msr_rw_dram(MTRR_FIX_64K_00000);
-	msr_rw_dram(MTRR_FIX_16K_80000);
-	for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++)
-		msr_rw_dram(i);
-
-	/* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_TOM2WB;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	x86_enable_cache();
-
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;