Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31903
Change subject: ec/google/wilco: Clear S0ix support bit at boot ......................................................................
ec/google/wilco: Clear S0ix support bit at boot
To ensure the power button functions as expected in firmware ensure that the EC is not in "S0ix supported OS" mode and expecting the power button to be handled by the virtual button interface.
BUG=b:128409889 TEST=Verify that the power button works at the developer screen when the system is rebooted from within Chrome OS. Also ensure that it works when external warm reset signal is asserted by H1.
Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/ec/google/wilco/Kconfig M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 3 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31903/1
diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index e905d5e..4202c1d 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -2,6 +2,7 @@ bool default n select EC_GOOGLE_COMMON_MEC + select EC_ACPI help Google Wilco Embedded Controller interface.
diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index a9caaec..0858e1c 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */
+#include <arch/acpi.h> #include <bootstate.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdint.h> #include <stdlib.h> @@ -55,6 +57,13 @@ if (!dev->enabled) return;
+ /* Disable S0ix support in EC RAM with ACPI EC interface */ + if (!acpi_is_wakeup_s3()) { + ec_set_ports(CONFIG_EC_BASE_ACPI_COMMAND, + CONFIG_EC_BASE_ACPI_DATA); + ec_write(EC_RAM_S0IX_SUPPORT, 0); + } + /* Print EC firmware information */ wilco_ec_print_all_info();
diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 53f6d0f..9c1685b 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,11 @@ KB_BIOS_PROGRESS = 0xc2, };
+enum ec_ram_addr { + /* Indicate support for S0ix */ + EC_RAM_S0IX_SUPPORT = 0xb8, +}; + enum set_acpi_mode_cmd { ACPI_OFF = 0, ACPI_ON
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31903 )
Change subject: ec/google/wilco: Clear S0ix support bit at boot ......................................................................
Patch Set 1: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31903 )
Change subject: ec/google/wilco: Clear S0ix support bit at boot ......................................................................
ec/google/wilco: Clear S0ix support bit at boot
To ensure the power button functions as expected in firmware ensure that the EC is not in "S0ix supported OS" mode and expecting the power button to be handled by the virtual button interface.
BUG=b:128409889 TEST=Verify that the power button works at the developer screen when the system is rebooted from within Chrome OS. Also ensure that it works when external warm reset signal is asserted by H1.
Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31903 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/ec/google/wilco/Kconfig M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 3 files changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index e905d5e..4202c1d 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -2,6 +2,7 @@ bool default n select EC_GOOGLE_COMMON_MEC + select EC_ACPI help Google Wilco Embedded Controller interface.
diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index a9caaec..0858e1c 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */
+#include <arch/acpi.h> #include <bootstate.h> #include <device/pnp.h> +#include <ec/acpi/ec.h> #include <pc80/keyboard.h> #include <stdint.h> #include <stdlib.h> @@ -55,6 +57,13 @@ if (!dev->enabled) return;
+ /* Disable S0ix support in EC RAM with ACPI EC interface */ + if (!acpi_is_wakeup_s3()) { + ec_set_ports(CONFIG_EC_BASE_ACPI_COMMAND, + CONFIG_EC_BASE_ACPI_DATA); + ec_write(EC_RAM_S0IX_SUPPORT, 0); + } + /* Print EC firmware information */ wilco_ec_print_all_info();
diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 53f6d0f..9c1685b 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,11 @@ KB_BIOS_PROGRESS = 0xc2, };
+enum ec_ram_addr { + /* Indicate support for S0ix */ + EC_RAM_S0IX_SUPPORT = 0xb8, +}; + enum set_acpi_mode_cmd { ACPI_OFF = 0, ACPI_ON
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)