Change in coreboot[master]: mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parameters

[Frank Wu (Code Review)]

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/25564

Change subject: mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parameters
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mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parameters

The commit enables DPTF function. The DPTF parameters are provided by thermal team.

BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot then check the parameters in DPTF ui tool

Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18
Signed-off-by: Frank Wu 
---
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
2 files changed, 118 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25564/1

diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index a04dd95..de5fb67 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -21,6 +21,9 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

+	# Enable DPTF
+	register "dptf_enable" = "1"
+
    # Enable S0ix
    register "s0ix_enable" = "1"

diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
index 216b76f..e5a71fa 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
@@ -13,4 +13,118 @@
  * GNU General Public License for more details.
  */

-/* Dummy file until DPTF support is added. */
+#define DPTF_CPU_PASSIVE	98
+#define DPTF_CPU_CRITICAL	125
+
+#define DPTF_CPU_ACTIVE_AC0	71
+#define DPTF_CPU_ACTIVE_AC1	69
+#define DPTF_CPU_ACTIVE_AC2	67
+#define DPTF_CPU_ACTIVE_AC3	65
+#define DPTF_CPU_ACTIVE_AC4	60
+
+#define DPTF_TSR0_SENSOR_ID     0
+#define DPTF_TSR0_SENSOR_NAME   "Thermal_Sensor_Remote_CPU"
+#define DPTF_TSR0_PASSIVE       81
+#define DPTF_TSR0_CRITICAL      125
+#define DPTF_TSR0_ACTIVE_AC0    62
+#define DPTF_TSR0_ACTIVE_AC1    60
+#define DPTF_TSR0_ACTIVE_AC2    55
+#define DPTF_TSR0_ACTIVE_AC3    50
+#define DPTF_TSR0_ACTIVE_AC4	45
+
+#define DPTF_TSR1_SENSOR_ID     1
+#define DPTF_TSR1_SENSOR_NAME   "Thermal_Sensor_Remote_PMIC"
+#define DPTF_TSR1_PASSIVE       78
+#define DPTF_TSR1_CRITICAL      125
+#define DPTF_TSR1_ACTIVE_AC0    60
+#define DPTF_TSR1_ACTIVE_AC1    55
+#define DPTF_TSR1_ACTIVE_AC2    50
+#define DPTF_TSR1_ACTIVE_AC3    45
+#define DPTF_TSR1_ACTIVE_AC4	40
+#endif
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+})
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {72,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {59,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {57,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {40,		0xFFFFFFFF,	3900,	90,	900}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.B0D4, 100, 100, 90, 72, 59, 40, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 100, 90, 72, 59, 40, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 100, 90, 72, 59, 40, 0, 0,
+			0, 0, 0
+	}
+})
+#endif
+
+Name (DTRT, Package () {
+
+	/* CPU Throttle Effect on CPU */
+	Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 0.1, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on TSR0 */
+	Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 0.1, 0, 0, 0, 0 },
+#if 0
+	/* Charger Throttle Effect on Charger (TSR1) */
+	Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+#endif
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		100	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		15000,	/* PowerLimitMinimum */
+		25000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		100	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>