Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and virtual wire mapping fix ......................................................................
soc/intel/common/gpio: support 16-bit CPU Port ID and virtual wire mapping fix
Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. Change cpu_port field to 16-bit width if the Kconfig is set. Support GPIO group for the virtual wire mapping whose bit position starts with non-zeo.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 3 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83981/1
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index de0546c..0dcc61e 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -63,4 +63,10 @@ SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser is 4 bits to support Native Function 1 to 15.
+config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID + bool + default n + help + Use 16-bit CPU port ID. + endif diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d49742d..2d3f800 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -1070,7 +1070,10 @@
offset += pad - comm->vw_entries[i].first_pad; *vw_index = comm->vw_base + offset / 8; - *vw_bit = offset % 8; + if (comm->vw_bit_start_pos) + *vw_bit = (offset + comm->vw_bit_start_pos[i]) % 8; + else + *vw_bit = offset % 8;
return true; } diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 8e60a16..fe455db 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -136,7 +136,11 @@ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ uint8_t port; /* PCR Port ID */ - uint8_t cpu_port; /* CPU Port ID */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID) + uint16_t cpu_port; /* Use 16-bit CPU Port ID */ +#else + uint8_t cpu_port; /* Use 8-bit CPU Port ID */ +#endif const struct reset_mapping *reset_map; /* PADRSTCFG logical to chipset mapping */ size_t num_reset_vals; @@ -148,6 +152,7 @@ * which they map to VW indexes (beginning with VW base) */ const struct vw_entries *vw_entries; + const uint8_t *vw_bit_start_pos; size_t num_vw_entries; };