[S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85289?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp/skx: Fix CPU init
......................................................................

soc/intel/xeon_sp/skx: Fix CPU init

Move CPU init closer to other SoC and CPX.

FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.

FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL

Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO

Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree

Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.

Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/xeon_sp/include/soc/msr.h
M src/soc/intel/xeon_sp/skx/cpu.c
3 files changed, 36 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/85289/2