[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting

[David Wu (Code Review)]

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro.

Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85519?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/alderlake: Add support for PCIe speed setting
......................................................................

soc/intel/alderlake: Add support for PCIe speed setting

This change provides config for devicetree to control PCIe speed

BUG=b:374205496
TEST=build pass

Change-Id: I32a9918a51faa903927a9646605a618744b527c0
Signed-off-by: David Wu 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 29 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85519/2