Ahamed Husni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67386 )
Change subject: Documentation: document the new smbus console feature ......................................................................
Documentation: document the new smbus console feature
Signed-off-by: Husni Faiz ahamedhusni73@gmail.com Change-Id: I50cafbbaaea133c9ea50131e455151287c96176a --- A Documentation/technotes/console.md M Documentation/technotes/index.md 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/67386/1
diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md new file mode 100644 index 0000000..9a84b5f --- /dev/null +++ b/Documentation/technotes/console.md @@ -0,0 +1,59 @@ +# coreboot Console + +coreboot supports multiple ways to access its console. +https://www.coreboot.org/Console_and_outputs + + +## SMBus Console + +SMBus is a two-wire interface which is based on the principles of operation +of I2C. SMBus, was first was designed to allow a battery to communicate with the +charger, the system host, and/or other power-related components in the system. + +Enable the SMBus console with `CONSOLE_I2C_SMBUS` Kconfig. Set +`CONSOLE_I2C_SMBUS_SLAVE_ADDRESS` and `CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER` +configuration values of the slave I2C device which you will use to capture +I2C packets. + +Currently SMBus console is supported in `BOOTBLOCK`, `ROMSTAGE` and `RAMSTAGE`. + +Modern computer Random Access Memory (RAM) slot has SMBus in it according to +the JEDEC standards. We can use a breakoutboard to expose those SMBus pins. +Some mainboard have SMBus pins in the PCIe slot as well. + +This feature has been tested on the following platforms: +```eval_rst ++------------------------------------+-------------------------------+ +| Platform | Support | ++====================================+===============================+ +| GA-H61M-S2PV + Intel Ivy Bridge | BOOTBLOCK, ROMSTAGE, RAMSTAGE | ++---------------------+----------------------------------------------+ +``` + +A minimal DDR3 DIMM breakout board with only the SDA(Data line) and +SCL(Clock line) pins of I2C/SMBus can be found +[here](https://github.com/drac98/ram-breakout-board). + +NOTE: +To capture the I2C packets, an I2C slave device is required. The easiest way to +capture the log message is to use a I2C to UART converter chip with a UART to +USB converter chip. The setup would be as follows. +```text + +---------+ +-------------+ +-------------+ + + PC +--------+ UART to USB +--------+ I2C to UART | + +---------+ +-------------+ +-------------+ + | | +------------------------------------------------------------+-- System Management +----------------------------------------------------------+---- Bus +``` + +Watch this [video](https://youtu.be/Q0dK41n9db8) to see how it is set up. + +If you are using a `SC16IS750` I2C to UART converter chip, you can enable the +`SC16IS750_INIT` option to initialize the chip. + +If not we can use a Beagleboard or an Arduino as an I2C slave device. + +This feature was added as part of a GSoC 2022 project. Checkout the +[coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-382736...) +blog post for more details. \ No newline at end of file diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index fda8bd6..da5b864 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -5,3 +5,4 @@ * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) * [Unit Test Code Coverage](2021-05-code-coverage.md) * [Address Sanitizer](asan.md) +* [coreboot Consoles](console.md)