Change in ...coreboot[master]: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33382
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 30 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/1
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 1d22046..2ca6dfb 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,7 +14,9 @@ */
#include <arch/acpi.h> +#include <bootstate.h> #include <drivers/vpd/vpd.h> +#include <gpio.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> @@ -77,3 +79,10 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +static void ssd_reset(void* unused) +{ + gpio_set(GPP_H12, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ssd_reset, NULL); diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index 20eee7f..7b6c96f 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */
+#include <delay.h> #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <intelblocks/pmclib.h> +#include <gpio.h>
static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -57,6 +61,19 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct chipset_power_state *ps = pmc_get_power_state(); + + if(ps) { + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) { + gpio_set(GPP_H13, 0); + mdelay(75); + gpio_set(GPP_H13, 1); + } + else { + gpio_set(GPP_H12, 1); + } + } + wilco_ec_romstage_init();
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index ff0240c..a0d21b4 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -16,6 +16,7 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
+ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_NC(GPP_A0, NONE), @@ -240,7 +241,6 @@ static const struct pad_config early_gpio_table[] = { /* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ @@ -252,7 +252,7 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ };
const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 78db12e..80d68d4 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -229,7 +229,7 @@ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* SSD RESET pin will stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ //PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -240,7 +240,7 @@ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ };
const struct pad_config *variant_gpio_table(size_t *num)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/33382/1/src/mainboard/google/sarien/ramstage... File src/mainboard/google/sarien/ramstage.c:
https://review.coreboot.org/#/c/33382/1/src/mainboard/google/sarien/ramstage... PS1, Line 83: static void ssd_reset(void* unused) "foo* bar" should be "foo *bar"
https://review.coreboot.org/#/c/33382/1/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/1/src/mainboard/google/sarien/romstage... PS1, Line 66: if(ps) { space required before the open parenthesis '('
https://review.coreboot.org/#/c/33382/1/src/mainboard/google/sarien/romstage... PS1, Line 72: else { else should follow close brace '}'
Hello Roy Mingi Park, Duncan Laurie,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#2).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 29 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/2
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33382/2/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/2/src/mainboard/google/sarien/romstage... PS2, Line 74: } What should we do if ps is NULL, set Power and Reset high?
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#3).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 27 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/3
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... File src/mainboard/google/sarien/ramstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 83: ssd_reset maybe ssd_deassert_reset() to be clear what it is doing.
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 85: GPP_H12 Since this is used in multiple places it is probably a good idea to add something to variant/gpio.h like
#define GPIO_SSD_RESET GPP_H12 #define GPIO_SSD_POWER GPP_H13
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 87: extra newline
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 67: ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR) soc/intel/cannonlake/pmutil.c:soc_prev_sleep_state() should be initializing ps->prev_sleep_state to ACPI_S5 based on this same check. Would it be possible to use that or even acpi_get_sleep_type() instead?
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 69: 75 Make this a #define.
Sigh, 75ms to every cold boot...
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#4).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/4
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... PS4, Line 24: * space before *
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... PS4, Line 72: gpio_set(GPIO_SSD_RESET, 1); Doesn't GPIO_SSD_RESET get deasserted in BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE) step anyway? Is this just to deassert the SSD reset earlier on a warm reboot?
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... File src/mainboard/google/sarien/ramstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 83: ssd_reset
maybe ssd_deassert_reset() to be clear what it is doing.
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 85: GPP_H12
Since this is used in multiple places it is probably a good idea to add something to variant/gpio. […]
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/ramstage... PS3, Line 87:
extra newline
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 67: ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)
soc/intel/cannonlake/pmutil. […]
Done
https://review.coreboot.org/#/c/33382/3/src/mainboard/google/sarien/romstage... PS3, Line 69: 75
Make this a #define. […]
HW engineer said 50ms should be okay, so I reduced it. If we can have 2 early gpio tables (warm reset / cold reset), we could potentially get rid of this delay, but that will require more testing. I wasn't able to detect warm/cold reset when setting early gpio tables, need to check that as well.
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#5).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/5
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... PS4, Line 24: *
space before *
Done
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... PS4, Line 72: gpio_set(GPIO_SSD_RESET, 1);
Doesn't GPIO_SSD_RESET get deasserted in BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE) step anyway? Is this […]
Yes,this is to keep the pulse shorter in warm reset case (Requirement was >10ms). So I deasserted before ramstage.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 5:
(1 comment)
The change seems largely fine now. At what point will your team have confidence and want to remove the WIP and commit it?
https://review.coreboot.org/#/c/33382/5/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/5/src/mainboard/google/sarien/romstage... PS5, Line 67: if (acpi_get_sleep_type() == ACPI_S5) { just a comment here to explain why this is necessary
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#6).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 35 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/6
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Patch Set 6:
(2 comments)
Patch Set 5:
(1 comment)
The change seems largely fine now. At what point will your team have confidence and want to remove the WIP and commit it?
We are running some cold/warm reboot cycles, I will check to see when will they be done.
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/4/src/mainboard/google/sarien/romstage... PS4, Line 72: gpio_set(GPIO_SSD_RESET, 1);
Yes,this is to keep the pulse shorter in warm reset case (Requirement was >10ms). […]
Done
https://review.coreboot.org/#/c/33382/5/src/mainboard/google/sarien/romstage... File src/mainboard/google/sarien/romstage.c:
https://review.coreboot.org/#/c/33382/5/src/mainboard/google/sarien/romstage... PS5, Line 67: if (acpi_get_sleep_type() == ACPI_S5) {
just a comment here to explain why this is necessary
Done
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#7).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 43 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/7
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#8).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 44 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/8
Hello Roy Mingi Park, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33382
to look at the new patch set (#9).
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
In order to fix,SSD can't be detected during cold-reset issue, add the required delays between powering the SSD and resetting it for cold and warm reboot cases.
BUG=b:132393441 TEST=Boot to OS with cold-reset
Change-Id: I03dabe1f75c761617c1129547342dff3047e101d Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 6 files changed, 44 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/9
Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33382 )
Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue ......................................................................
Abandoned
Not needed anymore
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Bora Guvendik (Code Review) -
build bot (Jenkins) (Code Review)
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Duncan Laurie (Code Review)