[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75750?usp=email )

Change subject: soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS
......................................................................

soc/intel/cmd/blk/cse: Add a config option to cache CSE version in CMOS

This patch adds a configuration option to store the CSE version in CMOS
memory. It also includes another configuration option to fix the CMOS
offset for the CSE version.

BUG=b:280722061
Test=Verified the changes nissa board.

Signed-off-by: Dinesh Gehlot 
Change-Id: I799f100ed4d319d93b06c68267fd2b03f2f5e7de
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/75750/1

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 54fd27c..e411d33 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -45,6 +45,22 @@
      Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
      to make `HECI1` device disable using private configuration register (PCR) write.

+config SOC_INTEL_PARTITION_FW_CMOS_OFFSET
+	int
+	default 72
+	depends on SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS
+	help
+	  This configuration option stores the starting offset of firmware partition versions in
+	  CMOS memory. The offset should be byte aligned and must leave enough memory to store
+	  required firmware partition versions.
+
+config SOC_INTEL_CACHE_CSE_VERSION_IN_CMOS
+	bool
+	default y
+	depends on SOC_INTEL_STORE_CSE_VERSION
+	help
+	  This configuration option stores CSE firmware version in CMOS memory.
+
 config SOC_INTEL_STORE_CSE_VERSION
    bool
    default n