Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Shuo Liu, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85557?usp=email )
Change subject: soc/intel/xeon_sp: Merge SKX and CPX ......................................................................
soc/intel/xeon_sp: Merge SKX and CPX
Start merging SKX and CPX into one codebase: - Create a new 14nm folder - Add new Kconfig: SOC_INTEL_XEON_SP_14NM - Add shared Kconfig settings - Add combined CPU driver - Add combined ACPI and romstage code
TODO: Merge additional code from skx/cpx folders.
TEST: Still boots on ocp/tiogapass.
Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/intel/cedarisland_crb/dsdt.asl M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl A src/soc/intel/xeon_sp/14nm/Kconfig A src/soc/intel/xeon_sp/14nm/Makefile.mk R src/soc/intel/xeon_sp/14nm/acpi/gpio.asl R src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl R src/soc/intel/xeon_sp/14nm/acpi/pch.asl R src/soc/intel/xeon_sp/14nm/acpi/pch_irq.asl R src/soc/intel/xeon_sp/14nm/acpi/pci_irqs.asl R src/soc/intel/xeon_sp/14nm/acpi/southcluster.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore_irq.asl R src/soc/intel/xeon_sp/14nm/cpu.c R src/soc/intel/xeon_sp/14nm/iio_ioapic.c A src/soc/intel/xeon_sp/14nm/romstage.c R src/soc/intel/xeon_sp/14nm/soc_acpi.c M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.mk D src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c D src/soc/intel/xeon_sp/skx/soc_acpi.c 26 files changed, 179 insertions(+), 535 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85557/1
diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 59ce66c..c08428f 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -22,7 +22,7 @@ { Device (PCI0) { - #include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl> + #include <soc/intel/xeon_sp/14nm/acpi/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl>
} diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 8442319..381204e 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -20,11 +20,11 @@ #include <cpu/intel/common/acpi/cpu.asl>
// CPX-SP ACPI tables - #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> + #include <soc/intel/xeon_sp/14nm/acpi/uncore.asl>
// LPC related entries Scope (_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> + #include <soc/intel/xeon_sp/14nm/acpi/pch.asl> } } diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 49f20f1..b448dfd 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,9 +15,9 @@ #include "acpi/platform.asl" #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> - #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> + #include <soc/intel/xeon_sp/14nm/acpi/uncore.asl> Scope (_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> + #include <soc/intel/xeon_sp/14nm/acpi/pch.asl> } } diff --git a/src/soc/intel/xeon_sp/14nm/Kconfig b/src/soc/intel/xeon_sp/14nm/Kconfig new file mode 100644 index 0000000..4e9d37b --- /dev/null +++ b/src/soc/intel/xeon_sp/14nm/Kconfig @@ -0,0 +1,92 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_XEON_SP_14NM + bool + select XEON_SP_COMMON_BASE + select NO_FSP_TEMP_RAM_EXIT + select UDK_202005_BINDING + help + Intel 14nm SoC (CPUID 506fx and CPUID 5065x) + +if SOC_INTEL_XEON_SP_14NM + +config MAX_SOCKET + int + default 2 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x1fff00 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. FSP-T reserves the upper 0x100 for + FspReservedBuffer. + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config STACK_SIZE + hex + default 0x4000 + +config IED_REGION_SIZE + hex + default 0x400000 + +config IFD_CHIPSET + string + default "lbg" + +config SOC_INTEL_COMMON_BLOCK_P2SB + def_bool y + +config CPU_BCLK_MHZ + int + default 100 + +# 14nm Xeon-SP have 2 IMCs, 3 channels per IMC, 2 DIMMs per channel +# Default value is set to two socket, full config. +config DIMM_MAX + default 24 + +# DDR4 +config DIMM_SPD_SIZE + default 512 + +config XEON_SP_HAVE_IIO_IOAPIC + bool + default y + +if INTEL_TXT + +config INTEL_TXT_SINIT_SIZE + hex + default 0x50000 + help + According to document number 572782 this needs to be 256KiB + for the SINIT module and 64KiB for SINIT data. + +config INTEL_TXT_HEAP_SIZE + hex + default 0xf0000 + help + This must be 960KiB according to 572782. + +endif # INTEL_TXT + +endif diff --git a/src/soc/intel/xeon_sp/14nm/Makefile.mk b/src/soc/intel/xeon_sp/14nm/Makefile.mk new file mode 100644 index 0000000..4dd57d6 --- /dev/null +++ b/src/soc/intel/xeon_sp/14nm/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_INTEL_XEON_SP_14NM),y) + +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/intel/microcode + +romstage-y += romstage.c +ramstage-y += cpu.c soc_acpi.c iio_ioapic.c + +endif ## CONFIG_SOC_INTEL_XEON_SP_14NM diff --git a/src/soc/intel/xeon_sp/acpi/gen1/gpio.asl b/src/soc/intel/xeon_sp/14nm/acpi/gpio.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/gpio.asl rename to src/soc/intel/xeon_sp/14nm/acpi/gpio.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl rename to src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/pch.asl b/src/soc/intel/xeon_sp/14nm/acpi/pch.asl similarity index 81% rename from src/soc/intel/xeon_sp/acpi/gen1/pch.asl rename to src/soc/intel/xeon_sp/14nm/acpi/pch.asl index 93d468a..5b53acb 100644 --- a/src/soc/intel/xeon_sp/acpi/gen1/pch.asl +++ b/src/soc/intel/xeon_sp/14nm/acpi/pch.asl @@ -3,7 +3,7 @@ /* This file should be included in the proper platform ACPI _SB PCI scope */
/* GPIO */ -#include <soc/intel/xeon_sp/acpi/gen1/gpio.asl> +#include <soc/intel/xeon_sp/14nm/acpi/gpio.asl>
/* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl b/src/soc/intel/xeon_sp/14nm/acpi/pch_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl rename to src/soc/intel/xeon_sp/14nm/acpi/pch_irq.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl b/src/soc/intel/xeon_sp/14nm/acpi/pci_irqs.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl rename to src/soc/intel/xeon_sp/14nm/acpi/pci_irqs.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl b/src/soc/intel/xeon_sp/14nm/acpi/southcluster.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl rename to src/soc/intel/xeon_sp/14nm/acpi/southcluster.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/uncore.asl b/src/soc/intel/xeon_sp/14nm/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/uncore.asl rename to src/soc/intel/xeon_sp/14nm/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl b/src/soc/intel/xeon_sp/14nm/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl rename to src/soc/intel/xeon_sp/14nm/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/14nm/cpu.c similarity index 82% rename from src/soc/intel/xeon_sp/skx/cpu.c rename to src/soc/intel/xeon_sp/14nm/cpu.c index 1becda8..e90c15a 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/14nm/cpu.c @@ -1,38 +1,40 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpigen.h> #include <assert.h> #include <console/console.h> #include <console/debug.h> #include <cpu/cpu.h> -#include <cpu/intel/cpu_ids.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/mp.h> #include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/turbo.h> #include <cpu/intel/smm_reloc.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> #include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> #include <intelpch/lockdown.h> #include <soc/msr.h> +#include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/soc_util.h> #include <soc/smmrelocate.h> +#include <soc/soc_util.h> #include <soc/util.h> #include <types.h> + #include "chip.h"
static const config_t *chip_config = NULL;
bool cpu_soc_is_in_untrusted_mode(void) { - /* IA_UNTRUSTED_MODE is not supported in Skylake */ + /* IA_UNTRUSTED_MODE is not supported on 14nm Xeon-SP */ return false; }
void cpu_soc_bios_done(void) { - /* IA_UNTRUSTED_MODE is not supported in Skylake */ + /* IA_UNTRUSTED_MODE is not supported on 14nm Xeon-SP */ }
static void xeon_configure_mca(void) @@ -40,10 +42,12 @@ msr_t msr; struct cpuid_result cpuid_regs;
- /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE - * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + /* + * Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA + */ cpuid_regs = cpuid(1); - if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + if ((cpuid_regs.edx & (1 << 7 | 1 << 14)) != (1 << 7 | 1 << 14)) return;
msr = rdmsr(IA32_MCG_CAP); @@ -53,9 +57,6 @@ wrmsr(IA32_MCG_CTL, msr); }
- /* TODO(adurbin): This should only be done on a cold boot. Also, some - of these banks are core vs package scope. For now every CPU clears - every bank. */ mca_configure(); }
@@ -70,20 +71,19 @@ * FSP-S updates microcodes serialized, so do the same. * */ -static void get_microcode_info(const void **microcode, int *parallel) +void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_microcode_find(); *parallel = 0; }
-static void xeon_sp_core_init(struct device *cpu) +static void each_cpu_init(struct device *cpu) { msr_t msr;
- printk(BIOS_INFO, "%s: cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + printk(BIOS_SPEW, "%s: cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", __func__, cpu_index(), cpu->path.apic.apic_id, cpu->path.apic.package_id); - assert(chip_config);
/* set MSR_PKG_CST_CONFIG_CONTROL - scope per core */ msr.hi = 0; @@ -107,8 +107,6 @@
/* * Set HWP base feature, EPP reg enumeration, lock thermal and msr - * TODO: Set LOCK_MISC_PWR_MGMT_MSR, Unexpected Exception if you - * lock & issue wrmsr on every thread * This is package level MSR. Need to check if it updates correctly on * multi-socket platform. */ @@ -150,7 +148,6 @@ wrmsr(MSR_CONFIG_TDP_CONTROL, msr);
msr = rdmsr(IA32_MISC_ENABLE); - /* Enable Fast Strings */ msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr);
@@ -190,16 +187,15 @@ }
static struct device_operations cpu_dev_ops = { - .init = xeon_sp_core_init, + .init = each_cpu_init, };
static const struct cpu_device_id cpu_table[] = { - /* Skylake-SP A0/A1 CPUID 0x506f0*/ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1, CPUID_EXACT_MATCH_MASK }, - /* Skylake-SP B0 CPUID 0x506f1*/ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0, CPUID_EXACT_MATCH_MASK }, - /* Skylake-SP 4 CPUID 0x50654*/ {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4, CPUID_EXACT_MATCH_MASK }, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0, CPUID_EXACT_MATCH_MASK }, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A1, CPUID_EXACT_MATCH_MASK }, CPU_TABLE_END };
@@ -237,15 +233,9 @@
/* * Do essential initialization tasks before APs can be fired up - * - * Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. */ static void pre_mp_init(void) { - printk(BIOS_DEBUG, "%s: entry\n", __func__); - x86_setup_mtrrs_with_detect(); x86_mtrr_check(); } @@ -262,9 +252,6 @@ } }
-/* - * CPU initialization recipe - */ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, @@ -277,8 +264,6 @@
void mp_init_cpus(struct bus *bus) { - FUNC_ENTER(); - const void *microcode_patch = intel_microcode_find();
if (!microcode_patch) @@ -292,10 +277,6 @@ * chip_info updated. Global chip_config is used as workaround */ chip_config = bus->dev->chip_info; - - /* calls src/cpu/x86/mp_init.c */ /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(bus, &mp_ops); - - FUNC_EXIT(); } diff --git a/src/soc/intel/xeon_sp/iio_ioapic.c b/src/soc/intel/xeon_sp/14nm/iio_ioapic.c similarity index 100% rename from src/soc/intel/xeon_sp/iio_ioapic.c rename to src/soc/intel/xeon_sp/14nm/iio_ioapic.c diff --git a/src/soc/intel/xeon_sp/14nm/romstage.c b/src/soc/intel/xeon_sp/14nm/romstage.c new file mode 100644 index 0000000..8d1bca9 --- /dev/null +++ b/src/soc/intel/xeon_sp/14nm/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/helpers.h> +#include <hob_iiouds.h> +#include <hob_memmap.h> +#include <soc/romstage.h> +#include <smbios.h> + +uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + +uint32_t get_max_capacity_mib(void) +{ + /* According to Dear Customer Letter it's 1.12 TB per processor. */ + return 1.12 * MiB * CONFIG_MAX_SOCKET; +} + +uint8_t get_max_dimm_count(void) +{ + return 2; +} + +uint8_t get_dram_type(const struct SystemMemoryMapHob *hob) +{ + return MEMORY_TYPE_DDR4; +} diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/14nm/soc_acpi.c similarity index 100% rename from src/soc/intel/xeon_sp/cpx/soc_acpi.c rename to src/soc/intel/xeon_sp/14nm/soc_acpi.c diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index c66b8ad..6f60772 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -2,8 +2,8 @@
ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
-subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg -subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg +subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx 14nm lbg +subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx 14nm lbg subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ibl
@@ -21,7 +21,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c ramstage-y += sad.c
smm-y += smihandler.c pmutil.c diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 51e545f..b26c83b 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,13 +2,11 @@
config SOC_INTEL_COOPERLAKE_SP bool - select XEON_SP_COMMON_BASE + select SOC_INTEL_XEON_SP_14NM select PLATFORM_USES_FSP2_2 select CACHE_MRC_SETTINGS - select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND - select UDK_202005_BINDING help Intel Cooper Lake-SP support
@@ -20,32 +18,10 @@ config FSP_FD_PATH default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd"
-config MAX_SOCKET - int - default 2 - config MAX_CPUS int default 255
-config PCR_BASE_ADDRESS - hex - default 0xfd000000 - help - This option allows you to select MMIO Base Address of sideband bus. - -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x1fff00 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. FSP-T reserves the upper 0x100 for - FspReservedBuffer. - config DCACHE_BSP_STACK_SIZE hex default 0x40000 @@ -65,18 +41,6 @@ allocated at 0xfe800000 (the CAR base) and consumes about 0x130000 bytes of memory.
-config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - -config STACK_SIZE - hex - default 0x4000 - config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK @@ -88,49 +52,4 @@ documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more.
-config IED_REGION_SIZE - hex - default 0x400000 - -config IFD_CHIPSET - string - default "lbg" - -config SOC_INTEL_COMMON_BLOCK_P2SB - def_bool y - -config CPU_BCLK_MHZ - int - default 100 - -# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel -# Default value is set to one socket, full config. -config DIMM_MAX - default 12 - -# DDR4 -config DIMM_SPD_SIZE - default 512 - -config XEON_SP_HAVE_IIO_IOAPIC - bool - default y - -if INTEL_TXT - -config INTEL_TXT_SINIT_SIZE - hex - default 0x50000 - help - According to document number 572782 this needs to be 256KiB - for the SINIT module and 64KiB for SINIT data. - -config INTEL_TXT_HEAP_SIZE - hex - default 0xf0000 - help - This must be 960KiB according to 572782. - -endif # INTEL_TXT - endif diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index c6639a2..b30795f 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -2,14 +2,11 @@
ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
-subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/intel/microcode - romstage-y += romstage.c soc_util.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c +ramstage-y += chip.c soc_util.c ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c deleted file mode 100644 index ae3f0fb..0000000 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpigen.h> -#include <assert.h> -#include <console/console.h> -#include <console/debug.h> -#include <cpu/cpu.h> -#include <cpu/intel/common/common.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/microcode.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> -#include <intelblocks/cpulib.h> -#include <intelblocks/mp_init.h> -#include <intelpch/lockdown.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/smmrelocate.h> -#include <soc/soc_util.h> -#include <soc/util.h> -#include <types.h> - -#include "chip.h" - -static const void *microcode_patch; - -static const config_t *chip_config = NULL; - -bool cpu_soc_is_in_untrusted_mode(void) -{ - /* IA_UNTRUSTED_MODE is not supported in Cooper Lake */ - return false; -} - -void cpu_soc_bios_done(void) -{ - /* IA_UNTRUSTED_MODE is not supported in Cooper Lake */ -} - -static void xeon_configure_mca(void) -{ - msr_t msr; - struct cpuid_result cpuid_regs; - - /* - * Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE - * and CPUID.(EAX=1):EDX[14]==1 MCA - */ - cpuid_regs = cpuid(1); - if ((cpuid_regs.edx & (1 << 7 | 1 << 14)) != (1 << 7 | 1 << 14)) - return; - - msr = rdmsr(IA32_MCG_CAP); - if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { - /* Enable all error logging */ - msr.lo = msr.hi = 0xffffffff; - wrmsr(IA32_MCG_CTL, msr); - } - - mca_configure(); -} - -/* - * On server platforms the FIT mechanism only updates the microcode on - * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases - * so do it serialized. - */ -void get_microcode_info(const void **microcode, int *parallel) -{ - *microcode = intel_microcode_find(); - *parallel = 0; -} - -static void each_cpu_init(struct device *cpu) -{ - msr_t msr; - - printk(BIOS_SPEW, "%s: cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, cpu_index(), cpu->path.apic.apic_id, - cpu->path.apic.package_id); - - /* - * Set HWP base feature, EPP reg enumeration, lock thermal and msr - * This is package level MSR. Need to check if it updates correctly on - * multi-socket platform. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ - msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | - LOCK_THERM_INT); - wrmsr(MSR_MISC_PWR_MGMT, msr); - } - - /* Enable Fast Strings */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= FAST_STRINGS_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - /* Enable Turbo */ - enable_turbo(); - - /* Enable speed step. */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - } - - /* Clear out pending MCEs */ - xeon_configure_mca(); - - /* Enable Vmx */ - set_vmx_and_lock(); - set_aesni_lock(); - - msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= BIT31; /* Lock it */ - wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = each_cpu_init, -}; - -static const struct cpu_device_id cpu_table[] = { - {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0, CPUID_EXACT_MATCH_MASK }, - {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A1, CPUID_EXACT_MATCH_MASK }, - CPU_TABLE_END -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; - -static void set_max_turbo_freq(void) -{ - msr_t msr, perf_ctl; - - FUNC_ENTER(); - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); - FUNC_EXIT(); -} - -/* - * Do essential initialization tasks before APs can be fired up - */ -static void pre_mp_init(void) -{ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - set_max_turbo_freq(); - - if (CONFIG(HAVE_SMI_HANDLER)) { - global_smi_enable(); - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) - pmc_lock_smi(); - } -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_platform_thread_count, - .get_smm_info = get_smm_info, - .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = smm_relocation_handler, - .get_microcode_info = get_microcode_info, - .post_mp_init = post_mp_init, -}; - -void mp_init_cpus(struct bus *bus) -{ - microcode_patch = intel_microcode_find(); - - if (!microcode_patch) - printk(BIOS_ERR, "microcode not found in CBFS!\n"); - - intel_microcode_load_unlocked(microcode_patch); - - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(bus, &mp_ops); - - /* - * chip_config is used in cpu device callback. Other than cpu 0, - * rest of the CPU devices do not have chip_info updated. - */ - chip_config = bus->dev->chip_info; -} diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 25dc4f6..51b462a 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -1,18 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h> -#include <cbmem.h> -#include <fsp/api.h> -#include <fsp/util.h> -#include <hob_iiouds.h> -#include <hob_memmap.h> -#include <soc/ddr.h> #include <soc/romstage.h> -#include <soc/pci_devs.h> -#include <soc/intel/common/smbios.h> #include <soc/soc_util.h> #include <static.h> -#include <string.h>
#include "chip.h"
@@ -21,25 +12,6 @@ /* Default weak implementation */ }
-uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -{ - switch (RasModesEnabled) { - case CH_INDEPENDENT: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case FULL_MIRROR_1LM: - case PARTIAL_MIRROR_1LM: - case FULL_MIRROR_2LM: - case PARTIAL_MIRROR_2LM: - return MEMORY_ARRAY_ECC_MULTI_BIT; - case RK_SPARE: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case CH_LOCKSTEP: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - default: - return MEMORY_ARRAY_ECC_MULTI_BIT; - } -} - void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -108,19 +80,3 @@ /* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); } - -uint32_t get_max_capacity_mib(void) -{ - /* According to Dear Customer Letter it's 1.12 TB per processor. */ - return 1.12 * MiB * CONFIG_MAX_SOCKET; -} - -uint8_t get_max_dimm_count(void) -{ - return MAX_IMC; -} - -uint8_t get_dram_type(const struct SystemMemoryMapHob *hob) -{ - return MEMORY_TYPE_DDR4; -} diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 970dba3..0a61a80 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -2,10 +2,8 @@
config SOC_INTEL_SKYLAKE_SP bool - select XEON_SP_COMMON_BASE + select SOC_INTEL_XEON_SP_14NM select PLATFORM_USES_FSP2_0 - select NO_FSP_TEMP_RAM_EXIT - select UDK_202005_BINDING help Intel Skylake-SP support
@@ -15,52 +13,14 @@ string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
-config MAX_SOCKET - int - default 2 - # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS int default 80
-config CPU_BCLK_MHZ - int - default 100 - -config PCR_BASE_ADDRESS - hex - default 0xfd000000 - help - This option allows you to select MMIO Base Address of sideband bus. - -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - config DCACHE_BSP_STACK_SIZE hex default 0x10000
-config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - -config IED_REGION_SIZE - hex - default 0x400000 - -config IFD_CHIPSET - string - default "lbg" - endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index 2955cbf..49f95b5 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -2,9 +2,6 @@
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
-subdirs-y += ../../../../cpu/intel/microcode -subdirs-y += ../../../../cpu/intel/turbo - postcar-y += soc_util.c
romstage-y += soc_util.c @@ -14,11 +11,9 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += soc_acpi.c ramstage-y += chip.c ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-y += soc_util.c -ramstage-y += cpu.c ramstage-y += ioapic.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index f66022d..b462f7b 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h> -#include <intelblocks/rtc.h> #include <soc/romstage.h> #include <soc/soc_util.h> #include <static.h> @@ -24,39 +23,4 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; -} - -uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -{ - switch (RasModesEnabled) { - case CH_INDEPENDENT: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case FULL_MIRROR_1LM: - case PARTIAL_MIRROR_1LM: - case FULL_MIRROR_2LM: - case PARTIAL_MIRROR_2LM: - return MEMORY_ARRAY_ECC_MULTI_BIT; - case RK_SPARE: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case CH_LOCKSTEP: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - default: - return MEMORY_ARRAY_ECC_MULTI_BIT; - } -} - -uint32_t get_max_capacity_mib(void) -{ - /* According to Dear Customer Letter it's 1.12 TB per processor. */ - return 1.12 * MiB * CONFIG_MAX_SOCKET; -} - -uint8_t get_max_dimm_count(void) -{ - return MAX_DIMM; -} - -uint8_t get_dram_type(const struct SystemMemoryMapHob *hob) -{ - return MEMORY_TYPE_DDR4; -} +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c deleted file mode 100644 index 2a9bd17..0000000 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpigen.h> -#include <arch/smp/mpspec.h> -#include <arch/vga.h> -#include <cpu/intel/turbo.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <intelblocks/acpi.h> -#include <soc/acpi.h> -#include <soc/iomap.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/soc_util.h> -#include <soc/util.h> - -int soc_madt_sci_irq_polarity(int sci) -{ - if (sci >= 20) - return MP_IRQ_POLARITY_LOW; - else - return MP_IRQ_POLARITY_HIGH; -} - -uint32_t soc_read_sci_irq_select(void) -{ - struct device *dev = PCH_DEV_PMC; - - if (!dev) - return 0; - - return pci_read_config32(dev, PMC_ACPI_CNT); -} - -void soc_fill_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SEALED_CASE); - fadt->flags |= ACPI_FADT_SLEEP_TYPE; - - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; - - /* PM Extended Registers */ - fill_fadt_extended_pm_io(fadt); -} - -void soc_power_states_generation(int core_id, int cores_per_package) -{ - generate_p_state_entries(core_id, cores_per_package); -}
-
Patrick Rudolph (Code Review)