HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16631
-gerrit
commit 429ae70000635897d098d2beb4b0d26f0d331895 Author: Elyes HAOUAS ehaouas@noos.fr Date: Sat Sep 17 20:48:29 2016 +0200
northbridge/intel/fsp_rangeley: Add space around operators
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 +- src/northbridge/intel/fsp_rangeley/northbridge.c | 4 ++-- src/northbridge/intel/fsp_rangeley/udelay.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 2ac1a23..6a33eda 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -170,7 +170,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) { soft_reset(); diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index b2ae3c4..4cb901a 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -88,8 +88,8 @@ static int add_fixed_resources(struct device *dev, int index)
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x " + "size = 0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index e599e00..5aca229 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h>
/** - * Intel Rangeley CPUs always run the TSC at BCLK=100MHz + * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.