Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email )
(
6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677) ......................................................................
mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
The MiTAC Computing Whitestone2 O-RAN CU/DU Edge Server is a compact and highly efficient 1U rackmount solution designed for edge computing in O-RAN (Open Radio Access Network) environments. Featuring support for the 4th Gen Intel® Xeon® Scalable Processor Edge Enhanced Product Family, it delivers robust performance with a single socket (LGA-4677) that supports up to 205W TDP. The server provides excellent memory capabilities with 8 DDR5 RDIMM slots supporting 4400 MHz speeds across 8 channels per CPU.
Working: - All eight DIMM slots - Serial port to emit spam - POST code display - Front USB 2.0 port - Front Intel E810 CAM1 (25Gbps x 4) - Front Intel E810 CAM2 (25Gbps x 4 / 10Gbps x 8) - M.2 2280/22110 slot x 2 (Gen3 x4) - Flashing internally with flashrom
Untested for now (i.e. should work, will eventually test): - Riser PCIe Gen.4 x16 slots x 2 (FHHL)
Others: - The board boots to Ubuntu 22.04.2 (5.15.0-1032-realtime) with all 40 cores (Intel 5433n) available. - FlexRAN 23.11 + DPDK 22.11.1 + ACC200 O-RU + O-DU long-run test pass.
Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Signed-off-by: Mark Chang mark.chang@mitaccomputing.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85532 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Shuo Liu shuo.liu@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A configs/config.mitaccomputing_ws_2 A src/mainboard/mitaccomputing/Kconfig A src/mainboard/mitaccomputing/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Kconfig A src/mainboard/mitaccomputing/whitestone-2/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Makefile.mk A src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl A src/mainboard/mitaccomputing/whitestone-2/board.fmd A src/mainboard/mitaccomputing/whitestone-2/board_info.txt A src/mainboard/mitaccomputing/whitestone-2/bootblock.c A src/mainboard/mitaccomputing/whitestone-2/devicetree.cb A src/mainboard/mitaccomputing/whitestone-2/dsdt.asl A src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h A src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h A src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h A src/mainboard/mitaccomputing/whitestone-2/mainboard.c A src/mainboard/mitaccomputing/whitestone-2/ramstage.c A src/mainboard/mitaccomputing/whitestone-2/romstage.c 18 files changed, 739 insertions(+), 0 deletions(-)
Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved
diff --git a/configs/config.mitaccomputing_ws_2 b/configs/config.mitaccomputing_ws_2 new file mode 100644 index 0000000..29a6c81 --- /dev/null +++ b/configs/config.mitaccomputing_ws_2 @@ -0,0 +1,28 @@ +# MiTAC Computing Whitestone-2 coreboot is modified from Intel ArcherCity CRB +# MiTAC Computing Whitestone-2 is a one socket CRB based on Intel. +# Sapphire Rapids Scalable Processor (SPR-SP) chipset. +# +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/config.config.mitaccomputing_ws_2 + +CONFIG_VENDOR_MITAC_COMPUTING=y +CONFIG_MAINBOARD_FAMILY="MiTAC Computing whitestone_2" +CONFIG_MAINBOARD_PART_NUMBER="MiTAC Computing WHITESTONE-2" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_VENDOR="MiTAC Computing Technology Corp." +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="MiTAC Computing Technology Corp." +CONFIG_BOARD_MITAC_COMPUTING_WHITESTONE_2=y +CONFIG_X2APIC_LATE_WORKAROUND=y +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/whitestone-2/bzImage" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/whitestone-2/Fsp_T.fd" +CONFIG_FSP_M_FILE="site-local/whitestone-2/Fsp_M.fd" +CONFIG_FSP_S_FILE="site-local/whitestone-2/Fsp_S.fd" +CONFIG_HAVE_IFD_BIN=y +CONFIG_IFD_BIN_PATH="site-local/whitestone-2/descriptor.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_BIN_PATH="site-local/whitestone-2/me.bin" +CONFIG_HAVE_GBE_BIN=y +CONFIG_GBE_BIN_PATH="site-local/whitestone-2/gbe.bin" diff --git a/src/mainboard/mitaccomputing/Kconfig b/src/mainboard/mitaccomputing/Kconfig new file mode 100644 index 0000000..c6a91e0 --- /dev/null +++ b/src/mainboard/mitaccomputing/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_MITAC_COMPUTING + +choice + prompt "Mainboard model" + +source "src/mainboard/mitaccomputing/*/Kconfig.name" + +endchoice + +source "src/mainboard/mitaccomputing/*/Kconfig" + +config MAINBOARD_VENDOR + default "MiTAC Computing" + +endif # VENDOR_MITAC_COMPUTING diff --git a/src/mainboard/mitaccomputing/Kconfig.name b/src/mainboard/mitaccomputing/Kconfig.name new file mode 100644 index 0000000..743b2db --- /dev/null +++ b/src/mainboard/mitaccomputing/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_MITAC_COMPUTING + bool "MiTAC Computing" diff --git a/src/mainboard/mitaccomputing/whitestone-2/Kconfig b/src/mainboard/mitaccomputing/whitestone-2/Kconfig new file mode 100644 index 0000000..03c4765 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Kconfig @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_MITAC_COMPUTING_WHITESTONE_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4677 + select CONSOLE_OVERRIDE_LOGLEVEL + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select IPMI_OCP + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select DRIVERS_ASPEED_AST2050 + select SOC_INTEL_SAPPHIRERAPIDS_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select MAINBOARD_USES_IFD_GBE_REGION + select VPD + select OCP_EWL + select OCP_VPD + +config MAINBOARD_DIR + string + default "mitaccomputing/whitestone-2" + +config MAINBOARD_PART_NUMBER + string + default "Whitestone 2" + +config MAINBOARD_FAMILY + default "Intel Eagle Stream Server" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_SOCKET + int + default 1 + +config DIMM_MAX + int + default 16 + +config UART_FOR_CONSOLE + int + default 0 + +config TTYS0_BAUD + default 115200 + +endif diff --git a/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name b/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name new file mode 100644 index 0000000..57d4133 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_MITAC_COMPUTING_WHITESTONE_2 + bool "Whitestone 2" diff --git a/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk b/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk new file mode 100644 index 0000000..4c7a7be --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl b/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl new file mode 100644 index 0000000..3918520 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/board.fmd b/src/mainboard/mitaccomputing/whitestone-2/board.fmd new file mode 100644 index 0000000..57ffccb --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/board.fmd @@ -0,0 +1,13 @@ +FLASH 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x7ed000 + SI_PT@0x7f0000 0x2810000 + } + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/board_info.txt b/src/mainboard/mitaccomputing/whitestone-2/board_info.txt new file mode 100644 index 0000000..c04abc4 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: MiTAC Computing +Board name: Whitestone 2 +Category: eval +ROM package: SOIC-16 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/mitaccomputing/whitestone-2/bootblock.c b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c new file mode 100644 index 0000000..ff38188 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2600 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For Whitestone-2, only SUART1 is used. + * Enable com1 (0x3f8), com2 (0x2f8) and superio (0x2e) + */ + lpc_open_pmio_window(0x3f8, 8); + lpc_open_pmio_window(0x2f8, 8); + lpc_open_pmio_window(0x2e, 2); + lpc_io_setup_comm_a_b(); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb b/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb new file mode 100644 index 0000000..e3bf1f4 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb @@ -0,0 +1,32 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + + device domain 0 on + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl b/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl new file mode 100644 index 0000000..272fca2 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // SPR-SP ACPI tables + #include <soc/intel/xeon_sp/spr/acpi/uncore.asl> + + // LPC related entries + Scope (_SB.PC00) + { + #include <soc/intel/xeon_sp/spr/acpi/pch.asl> + } +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h b/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h new file mode 100644 index 0000000..c68740d --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef WS_2_ONBOARD_H +#define WS_2_ONBOARD_H + +#define E810_CAM_NUMBER 2 +#define E810_CAM1_PORT_NUMBER 4 +#define E810_CAM2_PORT_NUMBER 8 +#define E810_CAM_PORT_NUMBER (E810_CAM1_PORT_NUMBER + E810_CAM2_PORT_NUMBER) +#define E810_CAM_PORT_NAME_LENGTH 15 +#define E810_CAM1_BUS_NUMBER 0x43 +#define E810_CAM2_BUS_NUMBER 0x44 + +#endif /* End of WS_2_ONBOARD_H */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h b/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h new file mode 100644 index 0000000..b823f01 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPPC_A ------- */ + /* PCH default for ESPI inter GPPC_A0-A9 */ + PAD_CFG_NF_OWNERSHIP(GPPC_A0, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A1, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A2, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A3, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A4, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A5, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A6, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A7, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A8, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A9, DN_20K, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_A10, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_A11, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A12, DN_20K, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_A13, 1, DEEP), + PAD_CFG_GPO(GPPC_A14, 1, DEEP), + PAD_CFG_GPO(GPPC_A15, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_A16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_A18, 1, DEEP), + PAD_CFG_GPO(GPPC_A19, 1, DEEP), + + /* ------- GPIO Group GPPC_B ------- */ + PAD_CFG_NF_OWNERSHIP(GPPC_B0, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B1, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B2, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B3, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B4, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B5, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B10, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B12, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B13, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B14, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B15, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B16, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B17, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B18, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B19, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B20, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B21, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B22, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B23, NONE, DEEP, NF4, ACPI), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPPC_C ------- */ + PAD_CFG_NF_OWNERSHIP(GPPC_C0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C1, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C2, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C4, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C5, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C10, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_C12, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_C13, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_C14, 1, DEEP), + PAD_CFG_GPO(GPPC_C15, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_C16, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_C17, 1, PLTRST), + PAD_CFG_GPO(GPPC_C18, 1, PLTRST), + PAD_CFG_NF_OWNERSHIP(GPPC_C19, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C20, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C21, NONE, DEEP, NF1, ACPI), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_NF_OWNERSHIP(GPP_D0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D1, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D2, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D9, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D12, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D14, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D15, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D16, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D17, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D20, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPP_D21, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D22, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E10, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E12, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E14, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E15, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E16, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_E18, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_GPO(GPP_I12, 1, DEEP), + PAD_CFG_GPO(GPP_I13, 1, DEEP), + PAD_CFG_GPO(GPP_I14, 1, DEEP), + PAD_CFG_GPO(GPP_I15, 1, DEEP), + PAD_CFG_GPO(GPP_I16, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPO(GPP_J2, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPP_J3, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_J4, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_J8, NONE, DEEP, NF1, ACPI), + + /* ------- GPIO Group GPP_L ------- */ + PAD_CFG_NF_OWNERSHIP(GPP_L0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_L1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_L2, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_L7, 1, DEEP), + PAD_CFG_GPO(GPP_L8, 1, DEEP), + + /* ------- GPIO Group GPP_M ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_N ------- */ + /* GPP_N1 - GPIO */ + PAD_NC(GPP_N1, NONE), + /* GPP_N4 - GPIO */ + PAD_NC(GPP_N4, NONE), + + /* ------- GPIO Group GPP_O ------- */ + /* GPP_O0 - GPIO */ + PAD_NC(GPP_O0, NONE), + /* GPP_O7 - GPIO */ + PAD_NC(GPP_O7, NONE), + + /* ------- GPIO Group GPPC_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_H15, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPPC_S ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_S1, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_S8, 1, DEEP), + PAD_CFG_GPO(GPPC_S9, 1, DEEP), + PAD_CFG_GPO(GPPC_S10, 1, DEEP), + PAD_CFG_GPO(GPPC_S11, 1, DEEP), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h b/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h new file mode 100644 index 0000000..5ea8260 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SPRSP_WS2_IIO_H_ +#define _SPRSP_WS2_IIO_H_ + +#include <defs_iio.h> +#include <soc/soc_util.h> + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = 0, \ + .SLOTHPSUP = 0, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = 1, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = 0, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + .PcieMaxPayload = 0x7, \ + .PciePortLinkSpeed = 0, \ + .DfxDnTxPresetGen3 = 0xFF \ + } + +#define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0) + +/* + * Whitestone 2 IIO PCIe Port Table + */ +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ws2_iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT(0, 1, 13), + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 48:03.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 48:05.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 48:07.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 59:03.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 59:05.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, /* 59:07.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + }, +}; + +static const UINT8 ws2_iio_bifur[CONFIG_MAX_SOCKET][5] = { + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxx8xxx8, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + }, +}; +#endif /* _SPRSP_WS2_IIO_H_ */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/mainboard.c b/src/mainboard/mitaccomputing/whitestone-2/mainboard.c new file mode 100644 index 0000000..8c3fe29 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/mainboard.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include "smbios_onboard.h" +#include <smbios.h> + +const char *e810_cam1_port_name[E810_CAM1_PORT_NUMBER] = { + "E810 CAM1 Port1", + "E810 CAM1 Port2", + "E810 CAM1 Port3", + "E810 CAM1 Port4", +}; + +const char *e810_cam2_port_name[E810_CAM2_PORT_NUMBER] = { + "E810 CAM2 Port1", + "E810 CAM2 Port2", + "E810 CAM2 Port3", + "E810 CAM2 Port4", + "E810 CAM2 Port5", + "E810 CAM2 Port6", + "E810 CAM2 Port7", + "E810 CAM2 Port8", +}; + +static int ws_2_onboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int data_length = 0; + int type_instance = 0; + + for (int i = 0; i < E810_CAM1_PORT_NUMBER; i++) { + data_length += smbios_write_type41( + current, handle, + e810_cam1_port_name[i], /* name */ + ++type_instance, /* instance */ + 0, /* segment */ + E810_CAM1_BUS_NUMBER, /* bus */ + 0, /* device */ + i, /* function */ + SMBIOS_DEVICE_TYPE_ETHERNET); /* device type */ + } + + for (int i = 0; i < E810_CAM2_PORT_NUMBER; i++) { + data_length += smbios_write_type41( + current, handle, + e810_cam2_port_name[i], /* name */ + ++type_instance, /* instance */ + 0, /* segment */ + E810_CAM2_BUS_NUMBER, /* bus */ + 0, /* device */ + i, /* function */ + SMBIOS_DEVICE_TYPE_ETHERNET); /* device type */ + } + return data_length; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_data = ws_2_onboard_smbios_data; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/mitaccomputing/whitestone-2/ramstage.c b/src/mainboard/mitaccomputing/whitestone-2/ramstage.c new file mode 100644 index 0000000..3372724 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/ramstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include "include/spr_ws_2_gpio.h" +#include <bootstate.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Emmitsburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void finalize_boot(void *unused) +{ + printk(BIOS_DEBUG, "FM_BIOS_POST_CMPLT_N cleared.\n"); + /* Clear FM_BIOS_POST_CMPLT_N */ + gpio_output(GPPC_C17, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/mitaccomputing/whitestone-2/romstage.c b/src/mainboard/mitaccomputing/whitestone-2/romstage.c new file mode 100644 index 0000000..748c78b --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/romstage.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include <soc/romstage.h> +#include <defs_cxl.h> +#include <defs_iio.h> +#include <sprsp_ws_2_iio.h> + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ + if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { + printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); + } else { + /* Set socket 0 IIO PCIe PE1 to CXL mode */ + /* eg. Protocol Auto Negotiation */ + mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL; + + mupd->FspmConfig.DfxCxlHeaderBypass = 0; + mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; + + mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */ + } +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + uint8_t val; + + /* Send FSP log message to SOL */ + if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) + mupd->FspmConfig.SerialIoUartDebugEnable = val; + else { + printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", + FSP_LOG, FSP_LOG_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + } + + /* Set Rank Margin Tool to disable. */ + mupd->FspmConfig.EnableRMT = 0x0; + /* Enable - Portions of memory reference code will be skipped + * when possible to increase boot speed on warm boots. + * Disable - Disables this feature. + * Auto - Sets it to the MRC default setting. + */ + mupd->FspmConfig.AttemptFastBoot = 0x1; + mupd->FspmConfig.AttemptFastBootCold = 0x1; + + /* Set Adv MemTest Option to 0. */ + mupd->FspmConfig.AdvMemTestOptions = 0x0; + /* Set MRC Promote Warnings to disable. + Determines if MRC warnings are promoted to system level. */ + mupd->FspmConfig.promoteMrcWarnings = 0x0; + /* Set Promote Warnings to disable. + Determines if warnings are promoted to system level. */ + mupd->FspmConfig.promoteWarnings = 0x0; + soc_config_iio(mupd, ws2_iio_pci_port, ws2_iio_bifur); + mainboard_config_iio(mupd); +}
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Lean Sheng Tan (Code Review)