Change in coreboot[master]: mainboard/google/puff: Enable pcie7 ep in dt

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/1

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 22e10c5..9ef39a6 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -59,6 +59,7 @@
    register "sdcard_cd_gpio" = "vSD3_CD_B"

device domain 0 on
+		device pci 07.0 on end # RTL8111H NIC.
    	device pci 15.0 off
    		# RFU - Reserved for Future Use.
    	end # I2C #0

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

Patch Set 1: Code-Review+1

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37804/1/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/puff/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/37804/1/src/mainboard/google/hatch/... 
PS1, Line 62: 07.0
This is not PCIe RP7.

[Edward O'Callaghan (Code Review)]

Hello Kangheui Won, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37804

to look at the new patch set (#2).

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

V.2: Include admendments from Kangheui.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/2

[Edward O'Callaghan (Code Review)]

Hello Kangheui Won, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37804

to look at the new patch set (#3).

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

V.2: Include admendments from Kangheui.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/puff/overridetree.cb
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/3

[Edward O'Callaghan (Code Review)]

Hello Kangheui Won, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37804

to look at the new patch set (#4).

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

V.2: Include admendments from Kangheui.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/puff/overridetree.cb
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/4

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

Patch Set 4:

(1 comment)
> Patch Set 1:
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/37804/1/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/puff/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/37804/1/src/mainboard/google/hatch/... 
PS1, Line 62: 07.0
> This is not PCIe RP7.

Ack

[Kangheui Won (Code Review)]

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

Patch Set 4: Code-Review+1

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

Patch Set 4: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
......................................................................

mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

V.2: Include admendments from Kangheui.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) 
Reviewed-by: Kangheui Won 
Reviewed-by: Patrick Georgi 
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/puff/overridetree.cb
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Kangheui Won: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 90c5ed3..3427ced 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -22,6 +22,8 @@
    select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
    select SOC_INTEL_COMETLAKE
    select SYSTEM_TYPE_LAPTOP
+	select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_PUFF
+	select RT8168_SET_LED_MODE if BOARD_GOOGLE_PUFF

if BOARD_GOOGLE_BASEBOARD_HATCH

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index ca6c818..d362b22 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -103,6 +103,13 @@
    	},
    }"

+	# PCIe port 7 for LAN
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpLtrEnable[6]" = "1"
+	# Uses CLK SRC 0
+	register "PcieClkSrcUsage[0]" = "6"
+	register "PcieClkSrcClkReq[0]" = "0"
+
    # GPIO for SD card detect
    register "sdcard_cd_gpio" = "vSD3_CD_B"

@@ -134,6 +141,7 @@
    		end
    	end #I2C #4
    	device pci 1a.0 on  end # eMMC
+		device pci 1c.6 on  end # PCI Express Port 7, RTL8111H Ethernet NIC.
    	device pci 1e.3 off end # GSPI #1
    end