Attention is currently required from: Felix Singer, Nico Huber, Damien Zammit, Tristan Corrick, Alexander Couzens, Patrick Rudolph, Felix Held. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52672 )
Change subject: src: Retype option API to use unsigned integers ......................................................................
src: Retype option API to use unsigned integers
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/console/init.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/lenovo/hybrid_graphics/romstage.c M src/ec/kontron/it8516e/ec.c M src/ec/lenovo/h8/bluetooth.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/wwan.c M src/ec/lenovo/pmh7/pmh7.c M src/include/option.h M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c M src/mainboard/getac/p470/early_init.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/kontron/986lcd-m/early_init.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/kontron/bsl6/variants/boxer26/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/lenovo/x60/smihandler.c M src/mainboard/roda/rk886ex/early_init.c M src/mainboard/siemens/chili/romstage.c M src/mainboard/siemens/chili/variants/chili/romstage.c M src/mainboard/supermicro/x10slm-f/mainboard.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/x4x/early_init.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c M src/superio/ite/it8720f/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83667hg-a/superio.c 58 files changed, 107 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52672/1
diff --git a/src/console/init.c b/src/console/init.c index fdc1467..a2ceb58 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -26,7 +26,7 @@ console_loglevel = get_console_loglevel();
if (!FIRST_CONSOLE) - console_loglevel = get_int_option("debug_level", console_loglevel); + console_loglevel = get_uint_option("debug_level", console_loglevel); }
int console_log_level(int msg_level) diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 888a2fd..38f6efc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -21,7 +21,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - disable_siblings = get_int_option("hyper_threading", disable_siblings); + disable_siblings = get_uint_option("hyper_threading", disable_siblings); } result = cpuid(1); /* Is hyperthreading supported */ diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index bae8a54..7a5e20d 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -25,7 +25,7 @@ return; }
- mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); + mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
if (mode == HYBRID_GRAPHICS_DISCRETE) { printk(BIOS_DEBUG, "Hybrid graphics:" diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 747c9b7..7cc1610 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -39,7 +39,7 @@ return; }
- mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU); + mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
if (mode == HYBRID_GRAPHICS_DISCRETE) { printk(BIOS_DEBUG, "Hybrid graphics:" diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 0b0e3ac..5288976 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -133,13 +133,13 @@ u8 fan_max = config->default_fan_max[fan_idx];
fanX_mode[3] = '1' + fan_idx; - fan_mode = get_int_option(fanX_mode, fan_mode); + fan_mode = get_uint_option(fanX_mode, fan_mode); if (!fan_mode) fan_mode = IT8516E_MODE_AUTO; it8516e_set_fan_mode(fan_idx, fan_mode);
fanX_target[3] = '1' + fan_idx; - fan_target = get_int_option(fanX_target, fan_target); + fan_target = get_uint_option(fanX_target, fan_target); switch (fan_mode) { case IT8516E_MODE_AUTO: printk(BIOS_DEBUG, @@ -173,8 +173,8 @@
fanX_min[3] = '1' + fan_idx; fanX_max[3] = '1' + fan_idx; - fan_min = get_int_option(fanX_min, fan_min); - fan_max = get_int_option(fanX_max, fan_max); + fan_min = get_uint_option(fanX_min, fan_min); + fan_max = get_uint_option(fanX_max, fan_max);
if (!fan_max || fan_max > 100) /* Constrain fan_max to 100% */ fan_max = 100; @@ -202,7 +202,7 @@ ec_set_ports(find_resource(dev, PNP_IDX_IO1)->base, find_resource(dev, PNP_IDX_IO0)->base);
- u8 systemp_type = get_int_option("systemp_type", config->default_systemp); + u8 systemp_type = get_uint_option("systemp_type", config->default_systemp); if (systemp_type >= IT8516E_SYSTEMP_LASTPLUSONE) systemp_type = IT8516E_SYSTEMP_NONE; it8516e_set_systemp_type(systemp_type); diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c index 463e0e3..16fc8dc 100644 --- a/src/ec/lenovo/h8/bluetooth.c +++ b/src/ec/lenovo/h8/bluetooth.c @@ -48,5 +48,5 @@ */ bool h8_bluetooth_nv_enable(void) { - return get_int_option("bluetooth", true); + return get_uint_option("bluetooth", true); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index be2eee6..e7e30fe 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -243,7 +243,7 @@ reg8 = conf->config1; if (conf->has_keyboard_backlight) { /* Default to both backlights */ - reg8 = (reg8 & 0xf3) | ((get_int_option("backlight", 0) & 0x3) << 2); + reg8 = (reg8 & 0xf3) | ((get_uint_option("backlight", 0) & 0x3) << 2); } ec_write(H8_CONFIG1, reg8); ec_write(H8_CONFIG2, conf->config2); @@ -253,14 +253,14 @@ beepmask1 = conf->beepmask1;
if (conf->has_power_management_beeps) { - if (get_int_option("power_management_beeps", 1) == 0) { + if (get_uint_option("power_management_beeps", 1) == 0) { beepmask0 = 0x00; beepmask1 = 0x00; } }
if (conf->has_power_management_beeps) { - if (get_int_option("low_battery_beep", 1)) + if (get_uint_option("low_battery_beep", 1)) beepmask0 |= 2; else beepmask0 &= ~2; @@ -292,14 +292,14 @@
ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
- h8_usb_always_on_enable(get_int_option("usb_always_on", 0)); + h8_usb_always_on_enable(get_uint_option("usb_always_on", 0));
- h8_wlan_enable(get_int_option("wlan", 1)); + h8_wlan_enable(get_uint_option("wlan", 1));
h8_trackpoint_enable(1); h8_usb_power_enable(1);
- int volume = get_int_option("volume", -1); + int volume = get_uint_option("volume", -1); if (volume >= 0 && !acpi_is_wakeup_s3()) ec_write(H8_VOLUME_CONTROL, volume);
@@ -311,16 +311,16 @@ h8_wwan_enable(val);
if (conf->has_uwb) - h8_uwb_enable(get_int_option("uwb", 1)); + h8_uwb_enable(get_uint_option("uwb", 1));
- h8_fn_ctrl_swap(get_int_option("fn_ctrl_swap", 0)); + h8_fn_ctrl_swap(get_uint_option("fn_ctrl_swap", 0));
- h8_sticky_fn(get_int_option("sticky_fn", 0)); + h8_sticky_fn(get_uint_option("sticky_fn", 0));
if (CONFIG(H8_HAS_PRIMARY_FN_KEYS)) - f1_to_f12_as_primary(get_int_option("f1_to_f12_as_primary", 1)); + f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1));
- h8_charge_priority(get_int_option("first_battery", PRIMARY_BATTERY)); + h8_charge_priority(get_uint_option("first_battery", PRIMARY_BATTERY));
h8_set_audio_mute(0); h8_mb_init(); diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index 90f6b47..685886f 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -46,5 +46,5 @@ */ bool h8_wwan_nv_enable(void) { - return get_int_option("wwan", true); + return get_uint_option("wwan", true); } diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index f32c9f1..ebcbcde 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -117,9 +117,9 @@ pmh7_backlight_enable(conf->backlight_enable); pmh7_dock_event_enable(conf->dock_event_enable);
- pmh7_touchpad_enable(get_int_option("touchpad", 1)); + pmh7_touchpad_enable(get_uint_option("touchpad", 1));
- pmh7_trackpoint_enable(get_int_option("trackpoint", 1)); + pmh7_trackpoint_enable(get_uint_option("trackpoint", 1));
printk(BIOS_INFO, "PMH7: ID %02x Revision %02x\n", pmh7_register_read(EC_LENOVO_PMH7_REG_ID), diff --git a/src/include/option.h b/src/include/option.h index 4de032b..e7db02e 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -10,7 +10,7 @@ enum cb_err cmos_set_option(const char *name, void *val); enum cb_err cmos_get_option(void *dest, const char *name);
-static inline enum cb_err set_int_option(const char *name, int value) +static inline enum cb_err set_uint_option(const char *name, unsigned int value) { if (CONFIG(USE_OPTION_TABLE)) return cmos_set_option(name, &value); @@ -18,10 +18,10 @@ return CB_CMOS_OTABLE_DISABLED; }
-static inline int get_int_option(const char *name, const int fallback) +static inline int get_uint_option(const char *name, const unsigned int fallback) { if (CONFIG(USE_OPTION_TABLE)) { - int value = 0; + unsigned int value = 0; if (cmos_get_option(&value, name) == CB_SUCCESS) return value; } diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index e20f4f4..1e91906 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -87,7 +87,7 @@ FchParams_reset->Mode = 6;
/* Read SATA speed setting from CMOS */ - FchParams_reset->SataSetMaxGen2 = get_int_option("sata_speed", 0); + FchParams_reset->SataSetMaxGen2 = get_uint_option("sata_speed", 0); printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2); }
@@ -102,7 +102,7 @@ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* Read SATA controller mode from CMOS */ - FchParams_env->Sata.SataClass = get_int_option("sata_mode", 0); + FchParams_env->Sata.SataClass = get_uint_option("sata_mode", 0);
switch ((SATA_CLASS)FchParams_env->Sata.SataClass) { case SataLegacyIde: diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index d7125d6..0bcd179 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -69,15 +69,15 @@ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver * and reboots, it will keep the USB3.0 speed */ - int usb3_mode = get_int_option("usb3_mode", 1); + int usb3_mode = get_uint_option("usb3_mode", 1); usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
/* Load USB3 pre-OS xHCI driver */ - int usb3_drv = get_int_option("usb3_drv", 1); + int usb3_drv = get_uint_option("usb3_drv", 1); usb3_drv &= 0x1; /* ensure it's 0/1 only */
/* Use USB3 xHCI streams */ - int usb3_streams = get_int_option("usb3_streams", 1); + int usb3_streams = get_uint_option("usb3_streams", 1); usb3_streams &= 0x1; /* ensure it's 0/1 only */
struct pei_data pd = { diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 9fdce75..bd30edf 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -656,7 +656,7 @@
ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP);
- int fan_speed_full = get_int_option("fan_full_speed", 0); + int fan_speed_full = get_uint_option("fan_full_speed", 0); if (fan_speed_full) { printk(BIOS_INFO, "Will set up fans to run at full speed\n"); ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP); diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 1ca9b79..c28d602 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -35,7 +35,7 @@ { int lpt_en = 0;
- if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */
// decode range diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index e1189a5..6fae52f 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -52,13 +52,13 @@ int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0;
- cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625); - //cpufan_temperature = get_int_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC); + cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625); + //cpufan_temperature = get_uint_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC);
- sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625); - //sysfan_temperature = get_int_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC); + sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625); + //sysfan_temperature = get_uint_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC);
// pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit // pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index ff3babb..5bed24b 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -15,7 +15,7 @@ { int lpt_en = 0;
- if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */
pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index f13731b..4cae5b8 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -50,11 +50,11 @@ int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0;
- cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625); + cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625);
- sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); - sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625); + sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED); + sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625);
nuvoton_hwm_select_bank(hwm_base, 0); pnp_write_hwm5_index(hwm_base, 0x59, 0x20); /* Diode Selection */ @@ -139,7 +139,7 @@ char cmos_option_name[] = "ethernetx"; snprintf(cmos_option_name, sizeof(cmos_option_name), "ethernet%01d", i); - int ethernet_disable = get_int_option(cmos_option_name, 0); + int ethernet_disable = get_uint_option(cmos_option_name, 0); if (!ethernet_disable) continue; printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i); diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index c5cba4d..f38734c 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -38,7 +38,7 @@
memory_params->DqPinsInterleaved = true;
- const uint8_t ht = get_int_option("hyper_threading", memory_params->HyperThreading); + const uint8_t ht = get_uint_option("hyper_threading", memory_params->HyperThreading); memory_params->HyperThreading = ht;
variant_memory_init_params(mupd); diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c index d352522..1985d4e 100644 --- a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -14,7 +14,7 @@
for (i = 0; i < 3; ++i) { nvram_var[sizeof(nvram_var) - 2] = '1' + i; - u8 eth_enable = get_int_option(nvram_var, 1); + u8 eth_enable = get_uint_option(nvram_var, 1); if (!eth_enable) { printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i); mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8)); diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 2d5063a..f8ef5383 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -149,7 +149,7 @@ /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif - unsigned int disable = get_int_option("ethernet1", 0); + unsigned int disable = get_uint_option("ethernet1", 0); if (disable) { struct device *nic = pcidev_on_root(0x1c, 2); if (nic) { @@ -157,7 +157,7 @@ nic->enabled = 0; } } - disable = get_int_option("ethernet2", 0); + disable = get_uint_option("ethernet2", 0); if (disable) { struct device *nic = pcidev_on_root(0x1c, 3); if (nic) { diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index ff041e7..efcd315 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -33,7 +33,7 @@
void mainboard_early_init(int s3resume) { - u8 enable_peg = get_int_option("enable_dual_graphics", 0); + u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
bool power_en = pmh7_dgpu_power_state();
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 817797f..e605453 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -22,7 +22,7 @@
void mb_late_romstage_setup(void) { - u8 enable_peg = get_int_option("enable_dual_graphics", 0); + u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
bool power_en = pmh7_dgpu_power_state();
diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 20ca060..e1a97f5 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -22,8 +22,8 @@ tmp70 = inb(0x70); tmp72 = inb(0x72);
- set_int_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)); - set_int_option("volume", ec_read(H8_VOLUME_CONTROL)); + set_uint_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)); + set_uint_option("volume", ec_read(H8_VOLUME_CONTROL));
outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 8f6cedd..76471eb 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -17,7 +17,7 @@ { int lpt_en = 0;
- if (get_int_option("lpt", 0)) + if (get_uint_option("lpt", 0)) lpt_en = LPT_LPC_EN; /* enable LPT */
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index 330d8afd..ddcc2cc 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -24,9 +24,9 @@ memupd->FspmConfig.EccSupport = 1; memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
- const uint8_t vtd = get_int_option("vtd", 1); + const uint8_t vtd = get_uint_option("vtd", 1); memupd->FspmTestConfig.VtdDisable = !vtd; - const uint8_t ht = get_int_option("hyper_threading", memupd->FspmConfig.HyperThreading); + const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); memupd->FspmConfig.HyperThreading = ht;
variant_romstage_params(memupd); diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index fadd2b7..d88301e 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -7,7 +7,7 @@
void variant_romstage_params(FSPM_UPD *const mupd) { - const uint8_t eth_enable = get_int_option("ethernet1", 1); + const uint8_t eth_enable = get_uint_option("ethernet1", 1);
if (!eth_enable) { printk(BIOS_DEBUG, "Disabling ethernet1.\n"); diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index b584e9b..98548e3 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -30,7 +30,7 @@
static void mainboard_enable(struct device *dev) { - if (get_int_option("hide_ast2400", false)) + if (get_uint_option("hide_ast2400", false)) hide_ast2400(); }
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index f7bdb28..7b0b1e5 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -116,7 +116,7 @@ sysinfo->ggc = 0x0002; else { /* 4 for 32MB, default if not set in CMOS */ - u8 gfxsize = get_int_option("gfx_uma_size", 4); + u8 gfxsize = get_uint_option("gfx_uma_size", 4);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, 2MB GTT + 2MB shadow GTT (0x0b00) else. */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b9c9441..d730b2e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -149,7 +149,7 @@ pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */ - gfxsize = get_int_option("gfx_uma_size", 2); /* 2 for 8MB */ + gfxsize = get_uint_option("gfx_uma_size", 2); /* 2 for 8MB */ /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8aa722c..0d014fb 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -710,7 +710,7 @@ if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff)); + pci_write_config8(dev, 0xf4, get_uint_option("tft_brightness", 0xff)); }
static void gma_generate_ssdt(const struct device *device) diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index d8e72b9..72c3028 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3102,7 +3102,7 @@ mchbar_write16(0x1170, 0xb880); mchbar_clrsetbits8(0x1210, ~0, 0x84);
- gfxsize = get_int_option("gfx_uma_size", 0); /* 0 for 32MB */ + gfxsize = get_uint_option("gfx_uma_size", 0); /* 0 for 32MB */
ggc = 0xb00 | ((gfxsize + 5) << 4);
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index df7dcb3..ae27d85 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,7 +25,7 @@ pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
/* Fetch VRAM size from CMOS option */ - reg8 = get_int_option("gfx_uma_size", 0); /* 0 for 8MB */ + reg8 = get_uint_option("gfx_uma_size", 0); /* 0 for 8MB */
/* Ensure the setting is valid */ if (reg8 > 6) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 51b8512..7acc5af 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -87,7 +87,7 @@ printk(BIOS_DEBUG, "Initializing Graphics...\n");
/* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ - gfxsize = get_int_option("gfx_uma_size", 0); + gfxsize = get_uint_option("gfx_uma_size", 0);
reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 1de9e28..410653d 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -39,7 +39,7 @@ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from CMOS, or default to 64 MiB */ - u8 gfxsize = get_int_option("gfx_uma_size", 6); + u8 gfxsize = get_uint_option("gfx_uma_size", 6); if (gfxsize > 12) gfxsize = 6; /* Need at least 4M for cbmem_top alignment */ diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 9981624..9605434 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -132,7 +132,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3); diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index 262ed47..dc35983 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -131,7 +131,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 935dd0c..b98c672 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -583,7 +583,7 @@ { bool on;
- const int state = get_int_option("power_on_after_fail", + const int state = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE);
switch (state) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 4ba8863..523854d 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -168,7 +168,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -210,7 +210,7 @@ outb(reg8, 0x61);
reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7ffef42..0148905 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -184,8 +184,8 @@ /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
- u8 me_state = get_int_option("me_state", 0); - u8 me_state_prev = get_int_option("me_state_prev", 0); + u8 me_state = get_uint_option("me_state", 0); + u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@@ -268,7 +268,7 @@ set the 'changed' bit here. */ if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { u8 new_state = me_state | CMOS_ME_STATE_CHANGED; - set_int_option("me_state_prev", new_state); + set_uint_option("me_state_prev", new_state); }
if (need_reset) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 3c5fcd1..6ad4cc2 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -182,8 +182,8 @@ /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
- u8 me_state = get_int_option("me_state", 0); - u8 me_state_prev = get_int_option("me_state_prev", 0); + u8 me_state = get_uint_option("me_state", 0); + u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@@ -267,7 +267,7 @@ set the 'changed' bit here. */ if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) { u8 new_state = me_state | CMOS_ME_STATE_CHANGED; - set_int_option("me_state_prev", new_state); + set_uint_option("me_state_prev", new_state); }
if (need_reset) { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 43ef9be..c9bc14c 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -35,7 +35,7 @@
/* Assign fixed resources for IDE legacy mode */
- u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); if (sata_mode != 2) return;
@@ -71,7 +71,7 @@ static void sata_set_resources(struct device *dev) { /* work around bug in pci_dev_set_resources(), it bails out on FIXED */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0); if (sata_mode == 2) { unsigned int i; for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { @@ -99,7 +99,7 @@ }
/* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* SATA configuration */
@@ -230,7 +230,7 @@ if (!config) return;
- u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index db034fc..489634f 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -99,7 +99,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 098af83..b79e100 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -94,7 +94,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; @@ -129,7 +129,7 @@ outb(reg8, 0x61);
reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 08019ac..0894f0d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -156,7 +156,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; @@ -192,7 +192,7 @@ outb(reg8, 0x61);
reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 667d81d..222df36 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -161,7 +161,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe; @@ -197,7 +197,7 @@ outb(reg8, 0x61);
reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index d2bee88..df74123 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -152,7 +152,7 @@ }
/* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * TODO: In contrast to ICH7 and PCH code we don't set @@ -227,7 +227,7 @@ if (!config) return;
- u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index f70636d..8e1e6f6 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -163,7 +163,7 @@ * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON); + const int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe; @@ -199,7 +199,7 @@ outb(reg8, 0x61);
reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 4d83388..c21c115 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -139,7 +139,7 @@ }
/* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * TODO: In contrast to ICH7 and PCH code we don't set @@ -205,7 +205,7 @@ return;
/* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index ae3233c..91c7d16 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -161,7 +161,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -203,7 +203,7 @@ outb(reg8, 0x61);
reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index dc3f1ff..171057e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -42,7 +42,7 @@ }
/* Default to AHCI */ - u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* SATA configuration */
@@ -174,7 +174,7 @@ if (!config) return;
- u8 sata_mode = get_int_option("sata_mode", 0); + u8 sata_mode = get_uint_option("sata_mode", 0);
/* * Set SATA controller mode early so the resource allocator can diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 71e4d74..a9a70b3 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -192,7 +192,7 @@ * * If the option is not existent (Laptops), use Kconfig setting. */ - const int pwr_on = get_int_option("power_on_after_fail", + const int pwr_on = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3); @@ -234,7 +234,7 @@ outb(reg8, 0x61);
reg8 = inb(0x70); - const int nmi_option = get_int_option("nmi", NMI_OFF); + const int nmi_option = get_uint_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 2c89a95..b1a9fbb 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -82,7 +82,7 @@ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const int s5pwr = get_int_option("power_on_after_fail", + const int s5pwr = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); outb(tmp70, 0x70); outb(tmp72, 0x72); diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index 0ecbddc..b2ac8a2 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -17,7 +17,7 @@
static void power_control_init(struct device *dev) { - int power_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_OFF); + int power_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_OFF); u8 value;
pnp_enter_conf_mode(dev); diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index b26954d..b0e00fb 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -47,7 +47,7 @@ break; case NCT5572D_ACPI: /* Set power state after power fail */ - power_status = get_int_option("power_on_after_fail", + power_status = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index e073dc3..d7f0a1f 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -68,7 +68,7 @@
npcd378_hwm_write_start(res->base);
- int fan_lvl = get_int_option("psu_fan_lvl", 3); + int fan_lvl = get_uint_option("psu_fan_lvl", 3); if (fan_lvl < 0 || fan_lvl > 7) fan_lvl = 3;
diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 2f0a3a4..a447931 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -23,7 +23,7 @@ static void init_acpi(struct device *dev) { u8 value; - int power_on = get_int_option("power_on_after_fail", 1); + int power_on = get_uint_option("power_on_after_fail", 1);
pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 5af2d37..fd510b1 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -23,7 +23,7 @@ static void init_acpi(struct device *dev) { u8 value; - int power_on = get_int_option("power_on_after_fail", 1); + int power_on = get_uint_option("power_on_after_fail", 1);
pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 5f96832..0a06898 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -47,7 +47,7 @@ break; case W83667HG_A_ACPI: /* Set power state after power fail */ - power_status = get_int_option("power_on_after_fail", + power_status = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pnp_enter_conf_mode(dev); pnp_set_logical_device(dev);
-
Angel Pons (Code Review)