Attention is currently required from: Zheng Bao.
Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/73410
to review the following change.
Change subject: WIP:amdfwtool: Add page ......................................................................
WIP:amdfwtool: Add page
Add command argument --body-page and --efs-page to set which 16M are these chunks located.
Change-Id: I9804ddc7fd2d59bc5b726de57d627cd785f1ed24 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M util/amdfwtool/amdfwtool.c 1 file changed, 71 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/73410/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index edac06a..3f70a5d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -89,6 +89,7 @@
#define AMD_ROMSIG_OFFSET 0x20000 #define MIN_ROM_KB 256 +#define DEFAULT_PAGE_SIZE (16 * 1024 * 1024)
#define _MAX(A, B) (((A) > (B)) ? (A) : (B)) #define ERASE_ALIGNMENT 0x1000U @@ -456,17 +457,20 @@
typedef struct _context { char *rom; /* target buffer, size of flash device */ + char *efs; + char *body; uint32_t rom_size; /* size of flash device */ uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current_pointer_saved; + uint32_t current_page; uint32_t current_table; } context;
#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) #define RUN_OFFSET_MODE(ctx, offset, mode) \ ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ - ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \ + ((mode) == AMD_ADDR_REL_BIOS ? (offset + (ctx).current_page * 16*1024*1024) : \ ((mode) == AMD_ADDR_REL_TAB ? (offset) - (ctx).current_table : (offset)))) #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \ @@ -526,6 +530,9 @@ { free(ctx->rom); ctx->rom = NULL; + if (ctx->body != NULL) + free(ctx->body); + ctx->body = NULL;
/* Free the filename. */ free_psp_firmware_filenames(amd_psp_fw_table); @@ -1803,6 +1810,7 @@ AMDFW_OPT_SIGNED_OUTPUT, AMDFW_OPT_SIGNED_ADDR, AMDFW_OPT_BODY_LOCATION, + AMDFW_OPT_BODY_PAGE, /* begin after ASCII characters */ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, @@ -1853,7 +1861,8 @@ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, - {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"body-page", required_argument, 0, AMDFW_OPT_BODY_PAGE }, /* other */ {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, @@ -2114,8 +2123,8 @@ context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ uint8_t sub = 0, instance = 0; - uint32_t body_location = 0; - uint32_t efs_location = 0; + uint32_t body_location = 0, body_page = 0xFFFFFFFF; + uint32_t efs_location = 0, efs_page = 0; bool any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; @@ -2345,6 +2354,15 @@ retval = 1; } break; + case AMDFW_OPT_BODY_PAGE: + body_page = (uint32_t)strtoul(optarg, &tmp, 10); + if (*tmp != '\0') { + fprintf(stderr, "Error: Body Location specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + body_page = 1; /* TODO: delete */ + break;
default: break; @@ -2379,6 +2397,14 @@ retval = 1; }
+ if (ctx.rom_size == 0) + ctx.rom_size = DEFAULT_PAGE_SIZE; + + if (body_page != 0xFFFFFFFF) + body_location %= DEFAULT_PAGE_SIZE; /* TODO: Delete */ + else + body_page = efs_page; /* If no body page is give, set it as efs page. */ + if ((ctx.rom_size % 1024 != 0) && !list_deps) { fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); @@ -2424,7 +2450,7 @@ }
if (body_location != efs_location && - body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { + body_location + body_page * DEFAULT_PAGE_SIZE < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); fprintf(stderr, " Require safe spacing of 256 bytes\n"); return 1; @@ -2477,16 +2503,19 @@ return 1; } } - ctx.rom = malloc(ctx.rom_size); - if (!ctx.rom) { + ctx.efs = malloc(ctx.rom_size); + if (!ctx.efs) { fprintf(stderr, "Error: Failed to allocate memory\n"); return 1; } - memset(ctx.rom, 0xFF, ctx.rom_size); + memset(ctx.efs, 0xFF, ctx.rom_size); + ctx.rom = ctx.efs;
romsig_offset = efs_location ? efs_location : AMD_ROMSIG_OFFSET; set_current_pointer(&ctx, romsig_offset);
+ ctx.current_page = efs_page; + amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; amd_romsig->imc_entry = 0; @@ -2517,9 +2546,18 @@ else printf("\n");
- if (efs_location != body_location) + if (efs_location != body_location) { + ctx.body = malloc(ctx.rom_size); + if (!ctx.body) { + fprintf(stderr, "Error: Failed to allocate memory\n"); + return 1; + } + memset(ctx.body, 0xFF, ctx.rom_size); + ctx.rom = ctx.body; + ctx.current_page = body_page; + set_current_pointer(&ctx, body_location); - else + } else set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware));
integrate_firmwares(&ctx, amd_romsig, amd_fw_table); @@ -2564,6 +2602,9 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); }
+ //ctx.address_mode = AMD_ADDR_REL_BIOS; + + switch (cb_config.soc_id) { case PLATFORM_UNKNOWN: amd_romsig->psp_directory = @@ -2598,6 +2639,8 @@ fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); }
+ //ctx.address_mode = AMD_ADDR_REL_TAB; + if (have_bios_tables(amd_bios_table)) { bios_directory_table *biosdir = NULL; if (cb_config.multi_level) { @@ -2631,6 +2674,8 @@ integrate_bios_firmwares(&ctx, biosdir, NULL, amd_bios_table, BHD_COOKIE, &cb_config); } + ///ctx.address_mode = AMD_ADDR_REL_BIOS; + switch (cb_config.soc_id) { case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: @@ -2661,6 +2706,7 @@ ctx.current - offset : sizeof(*amd_romsig); uint32_t ret_bytes;
+ ctx.rom = ctx.efs; ret_bytes = write(targetfd, BUFF_OFFSET(ctx, offset), bytes); if (bytes != ret_bytes) { fprintf(stderr, "Error: Writing to file %s failed\n", output); @@ -2675,6 +2721,7 @@ if (efs_location != body_location) { ssize_t bytes;
+ ctx.rom = ctx.body; bytes = write_body(output, BUFF_OFFSET(ctx, body_location), ctx.current - body_location, &ctx); if (bytes != ctx.current - body_location) { @@ -2684,5 +2731,6 @@ }
amdfwtool_cleanup(&ctx); + return retval; }