Hello Patrick Rudolph, Aaron Durbin, Nathaniel L Desimone, David Guckian, Subrata Banik, Matt DeVillier, build bot (Jenkins), Hannah Williams, Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29661
to look at the new patch set (#7).
Change subject: soc/intel/braswell: Add support for FSP MR2 ......................................................................
soc/intel/braswell: Add support for FSP MR2
In soc_silicon_init_params() and soc_display_silicon_init_params() fields are used which do not exist in MR2. Modify these function using the common 'pre MR2' and MR2 fields only. Configuration of 'pre MR2' fields is moved to mainboard.
BUG=NA TEST=Portwell PQ7-M107
Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/ramstage.c M src/mainboard/intel/strago/ramstage.c M src/soc/intel/braswell/chip.c 4 files changed, 87 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/7