Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich.
Tim Wawrzynczak has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/81082?usp=email )
Change subject: arch/riscv: Refactor SMP code ......................................................................
Patch Set 5:
(3 comments)
File src/arch/riscv/smp.c:
https://review.coreboot.org/c/coreboot/+/81082/comment/77561f0f_45d2b91c?usp... : PS5, Line 20: atomic_set(&HLS()->entry.sync_a, 0x01234567); // mark the hart as sleeping. Add a symbolic constant for this magic value?
https://review.coreboot.org/c/coreboot/+/81082/comment/cb19cedc_507063dd?usp... : PS5, Line 49: for (int i = 0; i < hart_count; i++) { There seems to be an assumption that hartid are always contiguous from 0, is that the case?
https://review.coreboot.org/c/coreboot/+/81082/comment/fefe5389_650bc197?usp... : PS5, Line 80: while (atomic_read(&OTHER_HLS(i)->entry.sync_a) != 0) should there be a timeout ?