Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 )
Change subject: device: Add support for PCIe Resizable BARs ......................................................................
Patch Set 2:
(4 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/61215/comment/26f8fad6_905334bd PS2, Line 656: For instance, if a device requests : 30 bits of address space (1 GiB), but this field is set to 29, then : the device will only be allocated 29 bits worth of address space (512 : MiB).
what will be the case when device may request for 28 bits address space (256MB) and default is set t […]
Correct, it is the default MAX number of bits of address space to hand out, so if the device requests less than that, that's fine and that's what it gets.
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/61215/comment/4e8ca019_68af794f PS2, Line 324: ctrl0
can we rename this to rebar_ctrl_reg or ctrl_reg. […]
This is the Resizable BAR Control Register for BAR 0; the field NBARs, although it is in the control register for each BAR, it only contains a valid value in BAR 0; i.e., you can't have less than 1 Resizable BAR (BAR 0 has to be supported if any are).
https://review.coreboot.org/c/coreboot/+/61215/comment/f3bc7b26_a3a2a130 PS2, Line 324: const uint32_t ctrl0 = pci_read_config32( : dev, offset + PCI_REBAR_CTRL_OFFSET);
nit: I believe it can fit even in single line?
Done
https://review.coreboot.org/c/coreboot/+/61215/comment/4e3a5083_77bd9bd1 PS2, Line 330: ctrl
regbar_cap_reg ?
this is the control register, but I'll give it a better name
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Tim Wawrzynczak (Code Review)