Change in coreboot[master]: mainboard/intel/glkrvp: Configure eSPI GPIOs to enable S0ix

[Shamile Khan (Code Review)]

Hello Hannah Williams,

I'd like you to do a code review. Please visit

https://review.coreboot.org/23742

to review the following change.

Change subject: mainboard/intel/glkrvp: Configure eSPI GPIOs to enable S0ix
......................................................................

mainboard/intel/glkrvp: Configure eSPI GPIOs to enable S0ix

Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams 
Signed-off-by: Shamile Khan 
---
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/23742/1

diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 0646bcf..81d6ba3 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -188,6 +188,9 @@
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD3*/
    PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1),/*LPC_CLKRUNB*/
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/
+#else
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 0, DEEP,  NONE, IGNORE, ENPU),/*LPC_CLKRUNB*/
 #endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/
    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/