Change in coreboot[master]: soc/amd/common/block/spi: Disable SPI Clock Pulldown

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63307 )

Change subject: soc/amd/common/block/spi: Disable SPI Clock Pulldown
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Patch Set 1:

(2 comments)

File src/soc/amd/common/block/include/amdblocks/acpimmio.h:

https://review.coreboot.org/c/coreboot/+/63307/comment/c7617bec_60f456d2 
PS1, Line 35: 0x90
> Does this apply to all the generations?

i don't see this in the stoneyridge bkdg or the picasso ppr. cezanne and sabrina ppr have this register and bit described

File src/soc/amd/common/block/spi/fch_spi.c:

https://review.coreboot.org/c/coreboot/+/63307/comment/3638ceff_4f11a61a 
PS1, Line 133: PM_SPI_CLK_PD_EN
> Did the default change on sabrina?

at least from the ppr both cezanne and sabrina have the spi clk pull-down enabled and the pull-up controlled by bit 10 in the same register disabled