John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp_up3
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..492054d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -113,6 +113,9 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
+ # Enable S0ix + register "s0ix_enable" = "1" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/1/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42954/1/src/mainboard/intel/tglrvp/... PS1, Line 117: register "s0ix_enable" = "1" trailing whitespace
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42954/2/src/mainboard/intel/tglrvp/... PS2, Line 117: register "s0ix_enable" = "1" trailing whitespace
Hello build bot (Jenkins), Wonkyu Kim, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42954
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp_up3
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42954/3/src/mainboard/intel/tglrvp/... PS3, Line 117: register "s0ix_enable" = "1" I think it's not TGLU only feature, can we also add this change for up4?
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42954
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp_up3
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/4
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42954
to look at the new patch set (#5).
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4. ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4.
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/5
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4. ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42954/3/src/mainboard/intel/tglrvp/... PS3, Line 117: register "s0ix_enable" = "1"
I think it's not TGLU only feature, can we also add this change for up4?
Done
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42954
to look at the new patch set (#6).
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/6
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 6: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42954/6//COMMIT_MSG@9 PS6, Line 9: tglrvp_up3 and up4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 6: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 6: Code-Review+2
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42954
to look at the new patch set (#7).
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp up3 and up4 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/7
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42954/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42954/6//COMMIT_MSG@9 PS6, Line 9: tglrvp_up3
and up4
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp up3 and up4 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 612a97d..b4a121a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -114,6 +114,9 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
+ # Enable S0ix + register "s0ix_enable" = "1" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7a97ad9..b08cd3c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -110,6 +110,9 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
+ # Enable S0ix + register "s0ix_enable" = "1" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"
-
build bot (Jenkins) (Code Review) -
Caveh Jalali (Code Review)
-
John Zhao (Code Review)
-
Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)
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Wonkyu Kim (Code Review)