Change in coreboot[master]: soc/mediatek/mt8183: add dphy reset after setting lanes number
jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36223 )
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
soc/mediatek/mt8183: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo effor.
BUG=b:139150763 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36223/1
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2b4fac7..d60abdb 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -392,6 +392,12 @@ } }
+static void mtk_dsi_reset_dphy(void) +{ + setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); + clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); +} + int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, const u8 *init_commands) { @@ -407,6 +413,8 @@ struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); + mdelay(1); + mtk_dsi_reset_dphy(); mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_clk_hs_mode_enable(); diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 9a00d1d..3052689 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -115,6 +115,7 @@ enum { DSI_RESET = BIT(0), DSI_EN = BIT(1), + DPHY_RESET = BIT(2), DSI_DUAL = BIT(4), };
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36223 )
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@9 PS1, Line 9: effor error?
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@12 PS1, Line 12: none kukui
https://review.coreboot.org/c/coreboot/+/36223/1/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/36223/1/src/soc/mediatek/common/dsi... PS1, Line 397: setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); : clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); no need to delay between them?
Hello Yu-Ping Wu, Julius Werner, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36223
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
soc/mediatek/mt8183: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo effor.
BUG=b:139150763 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36223/2
Hello Yu-Ping Wu, Julius Werner, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36223
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
soc/mediatek/mt8183: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo error.
BUG=b:139150763 BRANCH=kukui TEST=Boots correctly on kukui
Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36223/3
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36223 )
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@9 PS1, Line 9: effor
error?
Done
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@12 PS1, Line 12: none
kukui
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36223 )
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
Patch Set 3: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@9 PS1, Line 9: effor
error?
Ack
https://review.coreboot.org/c/coreboot/+/36223/1//COMMIT_MSG@12 PS1, Line 12: none
kukui
Ack
https://review.coreboot.org/c/coreboot/+/36223/1/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/36223/1/src/soc/mediatek/common/dsi... PS1, Line 397: setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); : clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
no need to delay between them?
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36223 )
Change subject: soc/mediatek/mt8183: add dphy reset after setting lanes number ......................................................................
soc/mediatek/mt8183: add dphy reset after setting lanes number
Add dphy reset after setting lanes number to avoid dphy fifo error.
BUG=b:139150763 BRANCH=kukui TEST=Boots correctly on kukui
Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9 Signed-off-by: Jitao Shi jitao.shi@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 2 files changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2b4fac7..d60abdb 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -392,6 +392,12 @@ } }
+static void mtk_dsi_reset_dphy(void) +{ + setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); + clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); +} + int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, const u8 *init_commands) { @@ -407,6 +413,8 @@ struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); + mdelay(1); + mtk_dsi_reset_dphy(); mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_clk_hs_mode_enable(); diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 9a00d1d..3052689 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -115,6 +115,7 @@ enum { DSI_RESET = BIT(0), DSI_EN = BIT(1), + DPHY_RESET = BIT(2), DSI_DUAL = BIT(4), };
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Hung-Te Lin (Code Review) -
jitao shi (Code Review)
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Patrick Georgi (Code Review)
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Yu-Ping Wu (Code Review)