Patch set updated for coreboot: 4ec8994 mainboard/intel/d510mo: Add Intel D510MO mainboard

[Damien Zammit]

Damien Zammit ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10074

-gerrit

commit 4ec89945e3db7fa98fc53f6345d588a394c319c8
Author: Damien Zammit 
Date:   Mon May 4 10:41:21 2015 +1000

mainboard/intel/d510mo: Add Intel D510MO mainboard

Board currently has no raminit, (uses Pineview minimal northbridge)
    Board boots to UART console.

Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
    Signed-off-by: Damien Zammit 
---
 src/mainboard/intel/d510mo/Kconfig                | 57 +++++++++++++
 src/mainboard/intel/d510mo/Kconfig.name           |  2 +
 src/mainboard/intel/d510mo/acpi/ec.asl            | 49 ++++++++++++
 src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 82 +++++++++++++++++++
 src/mainboard/intel/d510mo/acpi/mainboard.asl     | 34 ++++++++
 src/mainboard/intel/d510mo/acpi/superio.asl       | 45 +++++++++++
 src/mainboard/intel/d510mo/acpi_tables.c          | 66 +++++++++++++++
 src/mainboard/intel/d510mo/board_info.txt         |  5 ++
 src/mainboard/intel/d510mo/devicetree.cb          | 77 ++++++++++++++++++
 src/mainboard/intel/d510mo/dsdt.asl               | 55 +++++++++++++
 src/mainboard/intel/d510mo/hda_verb.c             |  7 ++
 src/mainboard/intel/d510mo/romstage.c             | 97 +++++++++++++++++++++++
 12 files changed, 576 insertions(+)

diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
new file mode 100644
index 0000000..aed13db
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -0,0 +1,57 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit 
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+if BOARD_INTEL_D510MO
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_INTEL_SOCKET_ATOM_D5XX
+	select CPU_MICROCODE_CBFS_NONE
+	select NORTHBRIDGE_INTEL_PINEVIEW
+	#select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_WINBOND_W83627THG
+	#select HAVE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select BROKEN_CAR_MIGRATE
+	#select USE_WATCHDOG_ON_BOOT
+	#select UDELAY_TSC
+	select EARLY_CBMEM_INIT
+	select BOARD_ROMSIZE_KB_1024
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config CBFS_SIZE
+	hex "Size of CBFS filesystem in ROM"
+	default 0x100000
+
+config MAINBOARD_DIR
+	string
+	default intel/d510mo
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "D510MO"
+
+config IRQ_SLOT_COUNT
+	int
+	default 7
+
+endif # BOARD_INTEL_D510MO
diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name
new file mode 100644
index 0000000..2df0dca
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_D510MO
+	bool "D510MO"
diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl
new file mode 100644
index 0000000..31c7001
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000
+		// for EC initialization before a driver
+		// is loaded
+	}
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+
+	// TODO EC Query methods
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..74c1ca0
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, 0, 21},
+		Package() { 0x0000ffff, 1, 0, 22},
+		Package() { 0x0000ffff, 2, 0, 23},
+		Package() { 0x0000ffff, 3, 0, 20},
+
+		Package() { 0x0001ffff, 0, 0, 22},
+		Package() { 0x0001ffff, 1, 0, 21},
+		Package() { 0x0001ffff, 2, 0, 20},
+		Package() { 0x0001ffff, 3, 0, 23},
+
+		Package() { 0x0002ffff, 0, 0, 18},
+		Package() { 0x0002ffff, 1, 0, 19},
+		Package() { 0x0002ffff, 2, 0, 17},
+		Package() { 0x0002ffff, 3, 0, 16},
+
+		Package() { 0x0003ffff, 0, 0, 19},
+		Package() { 0x0003ffff, 1, 0, 18},
+		Package() { 0x0003ffff, 2, 0, 21},
+		Package() { 0x0003ffff, 3, 0, 22},
+
+		Package() { 0x0005ffff, 0, 0, 17},
+		Package() { 0x0005ffff, 1, 0, 20},
+		Package() { 0x0005ffff, 2, 0, 22},
+		Package() { 0x0005ffff, 3, 0, 21},
+
+		Package() { 0x0008ffff, 0, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, _SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, _SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0002ffff, 3, _SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0003ffff, 1, _SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0003ffff, 2, _SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0003ffff, 3, _SB.PCI0.LPCB.LNKG, 0},
+
+		Package() { 0x0005ffff, 0, _SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 1, _SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0005ffff, 2, _SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0005ffff, 3, _SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0008ffff, 0, _SB.PCI0.LPCB.LNKE, 0},
+	})
+}
diff --git a/src/mainboard/intel/d510mo/acpi/mainboard.asl b/src/mainboard/intel/d510mo/acpi/mainboard.asl
new file mode 100644
index 0000000..73189be
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/mainboard.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (SLPB)
+{
+	Name(_HID, EisaId("PNP0C0E"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl
new file mode 100644
index 0000000..d615242
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/superio.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	Device (UAR1)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+
+	Device (UAR2)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+}
diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c
new file mode 100644
index 0000000..35c23a5
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi_tables.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt
new file mode 100644
index 0000000..192798a
--- /dev/null
+++ b/src/mainboard/intel/d510mo/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
new file mode 100644
index 0000000..7fca8b4
--- /dev/null
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -0,0 +1,77 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015  Damien Zammit 
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+chip northbridge/intel/pineview		# Northbridge
+  device cpu_cluster 0 on		# APIC cluster
+    chip cpu/intel/model_106cx		# CPU
+      device lapic 0 on end		# APIC
+    end
+  end
+  device domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host Bridge
+    device pci 2.0 on end		# Integrated graphics controller
+    chip southbridge/intel/i82801gx	# Southbridge
+      device pci 1b.0 on end		# Audio
+      device pci 1c.0 on end		# PCIe 1
+      device pci 1c.1 on end		# PCIe 2
+      device pci 1c.2 on end		# PCIe 3
+      device pci 1c.3 on end		# PCIe 4
+      device pci 1d.0 on end		# USB
+      device pci 1d.1 on end		# USB
+      device pci 1d.2 on end		# USB
+      device pci 1d.3 on end		# USB
+      device pci 1e.0 on end		# PCI bridge
+      device pci 1f.0 on		# ISA bridge
+        chip superio/winbond/w83627thg	# Super I/O
+          device pnp 4e.0 off end	# Floppy
+          device pnp 4e.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 4e.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 4e.3 on		# COM2
+	    io 0x60 = 0x2f8
+	    irq 0x70 = 3
+	  end
+          device pnp 4e.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 4e.a on end	# ACPI
+          device pnp 4e.b on		# HWM
+	    io 0x60 = 0x290
+	  end
+        end
+      end
+      device pci 1f.1 off end
+      device pci 1f.2 on end		# SATA
+      device pci 1f.3 on end		# SMbus
+      device pci 1f.4 off end
+      device pci 1f.5 off end
+      device pci 1f.6 off end
+    end
+  end
+end
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl
new file mode 100644
index 0000000..b6a1b8d
--- /dev/null
+++ b/src/mainboard/intel/d510mo/dsdt.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	//#include "acpi/platform.asl"
+
+	// global NVS and variables
+	//#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+	//#include <southbridge/intel/i82801gx/acpi/platform.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	//#include "acpi/mainboard.asl"
+
+	// Thermal Zone
+	//#include "acpi/thermal.asl"
+
+	Scope (_SB) {
+		Device (PCI0)
+		{
+			//#include <northbridge/intel/pineview/acpi/i945.asl>
+			//#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	//#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c
new file mode 100644
index 0000000..072a306
--- /dev/null
+++ b/src/mainboard/intel/d510mo/hda_verb.c
@@ -0,0 +1,7 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
new file mode 100644
index 0000000..391ecbd
--- /dev/null
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015  Damien Zammit 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <cpu/x86/bist.h>
+#include <superio/winbond/w83627thg/w83627thg.h>
+#include <superio/winbond/common/winbond.h>
+#include <lib.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+#define SUPERIO_DEV PNP_DEV(0x4e, 0)
+
+/* Early mainboard specific GPIO setup.
+ * We should use standard gpio.h eventually
+ */
+static void mb_gpio_init(void)
+{
+	device_t dev;
+
+	/* Southbridge GPIOs. */
+	dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+	pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+	outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+	outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+	outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+	outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+	outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
+	outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
+	outl(0x000300f3, DEFAULT_GPIOBASE + 0x38);
+}
+
+static void nm10_enable_lpc(void)
+{
+	/* Disable Serial IRQ */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+	/* Decode range */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+		CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+}
+
+void main(unsigned long bist)
+{
+	/*
+	const u8 spd_addrmap[4] = { 0x50, 0x51 };
+	*/
+
+	/* Disable watchdog timer */
+	RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+
+	/* Set southbridge and Super I/O GPIOs. */
+	mb_gpio_init();
+
+	nm10_enable_lpc();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
+
+	report_bist_failure(bist);
+	enable_smbus();
+	die("Waiting here\n");
+
+	/*
+	early_initialization();
+	sdram_initialize(0, spd_addrmap);
+	*/
+}