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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email )
Change subject: soc/intel/xeon_sp: Support multiple PCI segment groups
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Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/79878/comment/035b546c_d80532c4 :
PS2, Line 256: stack_enabled = false;
No, as that would leave the DSDT with missing resources. […]
Hi Rudolph,
SPR takes static DSDT template covering both XCC and MCC, where MCC has more accelerators than XCC. It is expected that for MCC it will proceed here, but for XCC it will skip the resource creation (otherwise, incorrect resources will be created for XCC).
For XCC, resource creation skipping will cause no _CRS be returned for the statically created accelerator DSDT host bridges, OS AML will return a warning but this will not cause a functionality error.
A similar case is for CXL. The SPR static DSDT template create CXL host bridge object for each IIO stack. However, when an IIO stack is not connected with an CXL card, the CXL resource creation will be incorrect and hence we need to skip as well. Similar, the _CRS skipping will cause OS AML to return a warning but not functional error.
We think the AML warning is an expected behavior for using static DSDT template covering SKU difference and CXL connection status.
If with original logic, can your MCC pass?
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