yuchi.chen@intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email )
Change subject: src/soc/intel/common/systemagent: improve systemagent ......................................................................
src/soc/intel/common/systemagent: improve systemagent
1. The TOLUD and TOUUD register in systemagent indicate address limit or address limit plus 1 on different SoCs. This patch add supports for it. 2. Make BDSM, BGSM and CAPID_A registers invisible for some SoC.
Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen yuchi.chen@intel.com --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 116 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/1
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 7bb55fe..09ae030 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -43,4 +43,52 @@ help Specify if the SOC has a PAM0 register
+config HAVE_CAPID_A_REGISTER + bool + default y + help + Specify if the SOC has the CAPID0_A register that holds DRAM informations. + +config TOUUD_LIMIT + bool + default n + help + Specify if the lower bits in top of upper usable DRAM register should be + treated as 1s. + +config TOUUD_ALIGNMENT + hex + default 0x100000 + +config TOLUD_LIMIT + bool + default n + help + Specify if the lower bits in top of lower usable DRAM register should be + treated as 1s. + +config TOLUD_ALIGNMENT + hex + default 0x100000 + +config HAVE_BDSM_BGSM_REGISTER + bool + default y + help + Specify if the SOC has BDSM and BGSM registres. + +config HAVE_TSEG_LIMIT_REGISTER + bool + default n + +config TSEG_ALIGNMENT + hex + default 0x100000 + +config HAVE_MULTIPLE_DOMAINS + bool + default n + help + Specify if the SOC has multiple PCIe domains. + endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index c26ee65..42efad2 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -74,6 +74,9 @@ { soc_systemagent_init(dev);
+ if (!CONFIG(HAVE_CAPID_A_REGISTER)) + return; + struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); if (m == NULL) return; @@ -124,10 +127,36 @@ * TSEG: This register contains the base address of TSEG DRAM memory */ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = { - { TOUUD, true, "TOUUD" }, - { TOLUD, false, "TOLUD" }, - { BGSM, false, "BGSM" }, - { TSEG, false, "TSEG" }, + { + .reg = TOUUD, + .is_64_bit = true, + .is_limit = CONFIG(TOUUD_LIMIT), + .description = "TOUUD", + .align = CONFIG_TOUUD_ALIGNMENT, + }, + { + .reg = TOLUD, + .is_64_bit = false, + .is_limit = CONFIG(TOLUD_LIMIT), + .description = "TOLUD", + .align = CONFIG_TOLUD_ALIGNMENT, + }, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) + { + .reg = BGSM, + .is_64_bit = false, + .is_limit = false, + .description = "BGSM", + .align = 1 * MiB, + }, +#endif + { + .reg = TSEG, + .is_64_bit = false, + .is_limit = false, + .description = "TSEG", + .align = CONFIG_TSEG_ALIGNMENT, + }, };
/* Read DRAM memory map register value through PCI configuration space */ @@ -142,8 +171,11 @@ }
value |= pci_read_config32(dev, entry->reg); - /* All registers are on a 1MiB granularity. */ - value = ALIGN_DOWN(value, 1 * MiB); + + if (entry->is_limit) + value = ALIGN_DOWN(value + entry->align, entry->align); + else + value = ALIGN_DOWN(value, entry->align);
*result = value; } @@ -269,6 +301,12 @@ { int index = 0;
+ /** + * If SoC has multiple PCIe domains, only reading resources from the first one. + */ + if (CONFIG(HAVE_MULTIPLE_DOMAINS) && dev->upstream->secondary != 0) + return; + /* Read standard PCI resources. */ pci_dev_read_resources(dev);
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 58d1113..b84615c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -58,7 +58,9 @@ enum { SA_TOUUD_REG, SA_TOLUD_REG, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) SA_BGSM_REG, +#endif SA_TSEG_REG, /* Must be last. */ MAX_MAP_ENTRIES @@ -68,12 +70,16 @@ * Set Fixed MMIO range * REG = Either PCI configuration space registers. * IS_64_BIT = If registers/offset is 64 bit. + * IS_LIMIT = If registers/offset indicates address limit or address limit plus 1. * DESCRIPTION = Name of the register/offset. + * ALIGN = Alignment boundary of the address. */ struct sa_mem_map_descriptor { unsigned int reg; bool is_64_bit; + bool is_limit; const char *description; + uint32_t align; };
#endif /* SOC_INTEL_COMMON_BLOCK_SA_DEF_H */ diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index aecdfbb..8a24202 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -130,8 +130,12 @@
uintptr_t sa_get_tolud_base(void) { - /* All regions concerned for have 1 MiB alignment. */ - return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB); + uint32_t tolud = pci_read_config32(SA_DEV_ROOT, TOLUD); + + if (CONFIG(TOLUD_LIMIT)) + return ALIGN_DOWN(tolud + CONFIG_TOLUD_ALIGNMENT, CONFIG_TOLUD_ALIGNMENT); + else + return ALIGN_DOWN(tolud, CONFIG_TOLUD_ALIGNMENT); }
uintptr_t sa_get_gsm_base(void) @@ -143,12 +147,22 @@ uintptr_t sa_get_tseg_base(void) { /* All regions concerned for have 1 MiB alignment. */ - return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TSEG), 1*MiB); + return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TSEG), CONFIG_TSEG_ALIGNMENT); }
size_t sa_get_tseg_size(void) { - return sa_get_gsm_base() - sa_get_tseg_base(); + if (!CONFIG(HAVE_TSEG_LIMIT_REGISTER)) { + return sa_get_gsm_base() - sa_get_tseg_base(); + } else { + /** + * Lower bits of TSEG limit are read as 0s but should be treated as 1s. + */ + return ALIGN_DOWN((pci_read_config32(SA_DEV_ROOT, TSEG + 4) + + CONFIG_TSEG_ALIGNMENT), + CONFIG_TSEG_ALIGNMENT) - + sa_get_tseg_base(); + } }
union dpr_register txt_get_chipset_dpr(void)