Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62903 )
Change subject: mb/google/skyrim: Add DXIO descriptors ......................................................................
Patch Set 4:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62903/comment/84ee5c8d_cb9fd28e PS3, Line 9: bouard board
https://review.coreboot.org/c/coreboot/+/62903/comment/44bb5d86_4d1078d0 PS3, Line 10: shematics schematics
https://review.coreboot.org/c/coreboot/+/62903/comment/d7dec241_527268fa PS3, Line 13: TEST=Builds just a build test is likely not sufficient; at least i'd prefer to have it verified on hardware that all pcie devices end up working
File src/mainboard/google/skyrim/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/62903/comment/73786acd_121b0e56 PS3, Line 49: //.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} // TODO: uncomment this when PSPP is working the commented out lines can be dropped for now. i also expect that we'll need different values here when pspp is working; probably {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
https://review.coreboot.org/c/coreboot/+/62903/comment/b0329b0d_69c50986 PS3, Line 54: .start_logical_lane = 0, the engine is unused, but the lanes overlap with the dxio descriptors before this one
File src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/62903/comment/4936d5d2_fbddaf38 PS3, Line 10: #define WLAN_DEVFN PCIE_GPP_2_0_DEVFN : #define SD_DEVFN PCIE_GPP_2_1_DEVFN i'm not certain if those device functions need to be swapped. there are requirements for the assignment of pcie device functions to root ports depending on the logical lane numbers within all devices with the same link width
-
Felix Held (Code Review)