[XS] Change in coreboot[main]: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83400?usp=email )

Change subject: soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
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soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds

The APOB NV size/base are embedded into the amdfw binary and read by
the PSP, and need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.

This fixes the issue of RAM training running on every boot on
non-vboot builds for Skyrim boards.

TEST=build/boot Skyrim (Frostflow), verify RAM training only
run on first boot after flashing.

Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Signed-off-by: Matt DeVillier 
---
M src/soc/amd/mendocino/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/83400/1

diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk
index a72116e..1b96ff1 100644
--- a/src/soc/amd/mendocino/Makefile.mk
+++ b/src/soc/amd/mendocino/Makefile.mk
@@ -122,7 +122,7 @@
 APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE)
 APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START)

-ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y)
+ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE)$(CONFIG_VBOOT),yy)
 # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE.
 # Else use RW_MRC_CACHE. This entry will be added in the RO section.
 APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE)