[M] Change in coreboot[master]: soc/mediatek: Unify PLL function names

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68622 )

(

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/mediatek: Unify PLL function names
......................................................................

soc/mediatek: Unify PLL function names

For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().

BUG=none
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen 
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin 
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/common/include/soc/pll_common.h
M src/soc/mediatek/common/pll.c
M src/soc/mediatek/mt8173/pll.c
M src/soc/mediatek/mt8183/pll.c
M src/soc/mediatek/mt8186/pll.c
M src/soc/mediatek/mt8188/pll.c
M src/soc/mediatek/mt8192/pll.c
M src/soc/mediatek/mt8195/dp_intf.c
M src/soc/mediatek/mt8195/pll.c
9 files changed, 41 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index 5c73a12..5484d67 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -64,14 +64,17 @@

DEFINE_BITFIELD(PLL_CON1, 31, 0)

+/* PLL internal interface */
 void pll_set_pcw_change(const struct pll *pll);
-void mux_set_sel(const struct mux *mux, u32 sel);
+void pll_mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
+
+/* PLL internal interface */
 void mt_pll_init(void);
 void mt_pll_raise_little_cpu_freq(u32 freq);
 void mt_pll_raise_cci_freq(u32 freq);
 void mt_pll_set_tvd_pll1_freq(u32 freq);
-void edp_mux_set_sel(u32 sel);
+void mt_pll_edp_mux_set_sel(u32 sel);
 void mt_pll_spmi_mux_select(void);
 void mt_pll_set_usb_clock(void);

diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c
index ca6226a..f13911b 100644
--- a/src/soc/mediatek/common/pll.c
+++ b/src/soc/mediatek/common/pll.c
@@ -5,7 +5,7 @@
 #include <soc/pll.h>
 #include <types.h>

-void mux_set_sel(const struct mux *mux, u32 sel)
+void pll_mux_set_sel(const struct mux *mux, u32 sel)
 {
    u32 mask = GENMASK(mux->mux_width - 1, 0);
    u32 val = read32(mux->reg);
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 7133fde..bbbb1f3 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -347,7 +347,7 @@
     * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
     *************/
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* enable scpsys clock off control */
    write32(&mtk_topckgen->clk_scp_cfg_0,
@@ -445,5 +445,5 @@
 void mt_mem_pll_mux(void)
 {
    /* CLK_CFG_0 */
-	mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */
+	pll_mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */
 }
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 0e96f4c..87562b1 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -344,7 +344,7 @@
     * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
     */
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* enable [14] dramc_pll104m_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c
index 9ab4f9c..a6165ef 100644
--- a/src/soc/mediatek/mt8186/pll.c
+++ b/src/soc/mediatek/mt8186/pll.c
@@ -468,7 +468,7 @@
    		INFRACFG_AO_PERI_BUS_REG0_2, 1);

for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* [4] SCP_CORE_CK_CG, [5] SEJ_CG */
    write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030);
@@ -528,7 +528,7 @@
 void mt_pll_spmi_mux_select(void)
 {
    /* 4: ulposc1_d10 */
-	mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4);
+	pll_mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4);
 }

u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c
index e88c192..a519fdd 100644
--- a/src/soc/mediatek/mt8188/pll.c
+++ b/src/soc/mediatek/mt8188/pll.c
@@ -573,7 +573,7 @@
     * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
     */
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* turn off unused clock in infra_ao */
    write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000);
@@ -633,9 +633,9 @@
    udelay(PLL_EN_DELAY);
 }

-void edp_mux_set_sel(u32 sel)
+void mt_pll_edp_mux_set_sel(u32 sel)
 {
-	mux_set_sel(&muxes[TOP_EDP_SEL], sel);
+	pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
 }

void mt_pll_set_usb_clock(void)
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index c9e2753..432b192 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -464,7 +464,7 @@
     * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
     */
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* enable [14] dramc_pll104m_ck */
    setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c
index 69a7740..ab2070e 100644
--- a/src/soc/mediatek/mt8195/dp_intf.c
+++ b/src/soc/mediatek/mt8195/dp_intf.c
@@ -221,7 +221,7 @@
    pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2));

mt_pll_set_tvd_pll1_freq(pll_rate / 4);
-	edp_mux_set_sel(clksrc);
+	mt_pll_edp_mux_set_sel(clksrc);

mtk_dpintf_enable(dpintf);

diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index 06b2156..792af7f 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -755,7 +755,7 @@
     * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
     */
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
-		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+		pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);

/* switch sram control to bypass mode for PCIE_MAC_P0 */
    setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
@@ -827,9 +827,9 @@
    udelay(PLL_EN_DELAY);
 }

-void edp_mux_set_sel(u32 sel)
+void mt_pll_edp_mux_set_sel(u32 sel)
 {
-	mux_set_sel(&muxes[TOP_EDP_SEL], sel);
+	pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
 }

u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)