Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email )
Change subject: soc/mediatek/mt8196: Add SPM loader ......................................................................
soc/mediatek/mt8196: Add SPM loader
This patch adds support for loading SPM firmware from CBFS to SPM SRAM and fix the SPM register definitions. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspends.
coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt)
TEST=build pass BUG=348147674
Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu wenzhen.yu@mediatek.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85599 Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 6 files changed, 1,357 insertions(+), 169 deletions(-)
Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 2133dbb..c5c6bf4 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -45,4 +45,9 @@ help The file name of the MediaTek SSPM firmware.
+config SPM_FIRMWARE + string + default "spm_firmware.pm" + help + The file name of the MediaTek SPM firmware. endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b61f7d9..a9ed31d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -53,6 +53,7 @@ ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c ramstage-y += soc.c +ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c sspm_sram.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c @@ -69,7 +70,8 @@ mcu-firmware-files := \ $(CONFIG_DPM_DM_FIRMWARE) \ $(CONFIG_DPM_PM_FIRMWARE) \ - $(CONFIG_SSPM_FIRMWARE) + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_SPM_FIRMWARE)
$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index fcb5fc8..96efa40 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -159,6 +159,7 @@ SSPM_CFG_BASE = IO_PHYS + 0x0C340000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, + VLP_DEVAPC_BASE = IO_PHYS + 0x0C550A00, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h index 7995a65..6c4a976 100644 --- a/src/soc/mediatek/mt8196/include/soc/pll.h +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -136,13 +136,15 @@ u32 reserved1[1]; u32 clk_cfg_update[3]; struct mtk_clk_cfg clk_cfg[23]; - u32 reserved2[16]; + u32 reserved2[8]; + u32 clk_scp_cfg; + u32 reserved3[7]; u32 clk26cali[2]; - u32 reserved3[3]; + u32 reserved4[3]; u32 clk_misc_cfg; - u32 reserved4[10]; + u32 reserved5[10]; u32 clk_dbg_cfg; - u32 reserved5[13]; + u32 reserved6[13]; u32 clk_prot_idle_reg; u32 clk_fenc_bypass_reg[3]; u32 clk_prot_idle_all_reg[3]; @@ -152,6 +154,7 @@ }; check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); check_member(mtk_topckgen_regs, clk_cfg[0], 0x0010); +check_member(mtk_topckgen_regs, clk_scp_cfg, 0x01A0); check_member(mtk_topckgen_regs, clk26cali[0], 0x01C0); check_member(mtk_topckgen_regs, clk_prot_idle_all_reg[0], 0x0248); check_member(mtk_topckgen_regs, clk_prot_spm_ck_en_reg, 0x026C); diff --git a/src/soc/mediatek/mt8196/include/soc/spm.h b/src/soc/mediatek/mt8196/include/soc/spm.h index b0f1264..5e6b784 100644 --- a/src/soc/mediatek/mt8196/include/soc/spm.h +++ b/src/soc/mediatek/mt8196/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h>
+#define INFRA_SW_CG (INFRACFG_AO_BASE + 0x60) + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) @@ -61,11 +63,8 @@ /* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
-/************************************** - * Config and Parameter - **************************************/ -#define SPM_SYSTEM_BASE_OFFSET 0x40000000 -#define POWER_ON_VAL1_DEF 0x003ffe24 +#define SPM_SYSTEM_BASE_OFFSET 0x0 +#define POWER_ON_VAL1_DEF 0x003ffe20 #define SPM_WAKEUP_EVENT_MASK_DEF 0xefffffff #define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff #define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff @@ -81,10 +80,15 @@ #define ARMPLL_CLK_SEL_DEF 0x3ff #define SPM_SYSCLK_SETTLE 0x60fe #define SPM_INIT_DONE_US 20 +#define PCM_WDT_TIMEOUT_S (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT_S) +#define AP_WDT_TIMEOUT_SUSPEND_S 5400 +#define PCM_TIMER_SUSPEND ((AP_WDT_TIMEOUT_SUSPEND_S - 30) * 32768) +#define SPM_FLAG_ENABLE_MT8196_ES_WA BIT(24) +#define SPM_FLAG_ENABLE_MT8196_EMI_ES_WA BIT(25) +#define MT_SPM_VERSION_ES 0x0 +#define MT_SPM_VERSION_CS 0x1
-/************************************** - * Definition and Declaration - **************************************/ /* SPM_IRQ_MASK */ #define ISRM_TWAM BIT(2) #define ISRM_PCM_RETURN BIT(3) @@ -192,13 +196,32 @@ u8 vrf18_state;
/* SPM_SRC_MASK_0 */ + u8 reg_apifr_mem_apsrc_req_mask_b; + u8 reg_apifr_mem_ddren_req_mask_b; + u8 reg_apifr_mem_emi_req_mask_b; + u8 reg_apifr_mem_infra_req_mask_b; + u8 reg_apifr_mem_pmic_req_mask_b; + u8 reg_apifr_mem_srcclkena_mask_b; + u8 reg_apifr_mem_vcore_req_mask_b; + u8 reg_apifr_mem_vrf18_req_mask_b; u8 reg_apu_apsrc_req_mask_b; u8 reg_apu_ddren_req_mask_b; u8 reg_apu_emi_req_mask_b; u8 reg_apu_infra_req_mask_b; u8 reg_apu_pmic_req_mask_b; u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_vcore_req_mask_b; u8 reg_apu_vrf18_req_mask_b; + u8 reg_audio_apsrc_req_mask_b; + u8 reg_audio_ddren_req_mask_b; + u8 reg_audio_emi_req_mask_b; + u8 reg_audio_infra_req_mask_b; + u8 reg_audio_pmic_req_mask_b; + u8 reg_audio_srcclkena_mask_b; + u8 reg_audio_vcore_req_mask_b; + u8 reg_audio_vrf18_req_mask_b; + + /* SPM_SRC_MASK_1 */ u8 reg_audio_dsp_apsrc_req_mask_b; u8 reg_audio_dsp_ddren_req_mask_b; u8 reg_audio_dsp_emi_req_mask_b; @@ -214,33 +237,18 @@ u8 reg_cam_pmic_req_mask_b; u8 reg_cam_srcclkena_mask_b; u8 reg_cam_vrf18_req_mask_b; - - /* SPM_SRC_MASK_1 */ u32 reg_ccif_apsrc_req_mask_b; - u32 reg_ccif_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv0_ddren_req_mask_b; - u8 reg_vlpcfg_rsv0_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_infra_req_mask_b; - u8 reg_vlpcfg_rsv0_pmic_req_mask_b; - u8 reg_vlpcfg_rsv0_srcclkena_mask_b; - u8 reg_vlpcfg_rsv0_vcore_req_mask_b; - u8 reg_vlpcfg_rsv0_vrf18_req_mask_b;
/* SPM_SRC_MASK_2 */ + u32 reg_ccif_emi_req_mask_b; u32 reg_ccif_infra_req_mask_b; - u32 reg_ccif_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv1_ddren_req_mask_b; - u8 reg_vlpcfg_rsv1_emi_req_mask_b; - u8 reg_vlpcfg_rsv1_infra_req_mask_b; - u8 reg_vlpcfg_rsv1_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_srcclkena_mask_b; - u8 reg_vlpcfg_rsv1_vcore_req_mask_b; - u8 reg_vlpcfg_rsv1_vrf18_req_mask_b;
/* SPM_SRC_MASK_3 */ + u32 reg_ccif_pmic_req_mask_b; u32 reg_ccif_srcclkena_mask_b; + + /* SPM_SRC_MASK_4 */ + u32 reg_ccif_vcore_req_mask_b; u32 reg_ccif_vrf18_req_mask_b; u8 reg_ccu_apsrc_req_mask_b; u8 reg_ccu_ddren_req_mask_b; @@ -251,7 +259,7 @@ u8 reg_ccu_vrf18_req_mask_b; u8 reg_cg_check_apsrc_req_mask_b;
- /* SPM_SRC_MASK_4 */ + /* SPM_SRC_MASK_5 */ u8 reg_cg_check_ddren_req_mask_b; u8 reg_cg_check_emi_req_mask_b; u8 reg_cg_check_infra_req_mask_b; @@ -259,6 +267,32 @@ u8 reg_cg_check_srcclkena_mask_b; u8 reg_cg_check_vcore_req_mask_b; u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_cksys_apsrc_req_mask_b; + u8 reg_cksys_ddren_req_mask_b; + u8 reg_cksys_emi_req_mask_b; + u8 reg_cksys_infra_req_mask_b; + u8 reg_cksys_pmic_req_mask_b; + u8 reg_cksys_srcclkena_mask_b; + u8 reg_cksys_vcore_req_mask_b; + u8 reg_cksys_vrf18_req_mask_b; + u8 reg_cksys_1_apsrc_req_mask_b; + u8 reg_cksys_1_ddren_req_mask_b; + u8 reg_cksys_1_emi_req_mask_b; + u8 reg_cksys_1_infra_req_mask_b; + u8 reg_cksys_1_pmic_req_mask_b; + u8 reg_cksys_1_srcclkena_mask_b; + u8 reg_cksys_1_vcore_req_mask_b; + u8 reg_cksys_1_vrf18_req_mask_b; + + /* SPM_SRC_MASK_6 */ + u8 reg_cksys_2_apsrc_req_mask_b; + u8 reg_cksys_2_ddren_req_mask_b; + u8 reg_cksys_2_emi_req_mask_b; + u8 reg_cksys_2_infra_req_mask_b; + u8 reg_cksys_2_pmic_req_mask_b; + u8 reg_cksys_2_srcclkena_mask_b; + u8 reg_cksys_2_vcore_req_mask_b; + u8 reg_cksys_2_vrf18_req_mask_b; u8 reg_conn_apsrc_req_mask_b; u8 reg_conn_ddren_req_mask_b; u8 reg_conn_emi_req_mask_b; @@ -268,12 +302,23 @@ u8 reg_conn_srcclkenb_mask_b; u8 reg_conn_vcore_req_mask_b; u8 reg_conn_vrf18_req_mask_b; + u8 reg_corecfg_rsv0_apsrc_req_mask_b; + u8 reg_corecfg_rsv0_ddren_req_mask_b; + u8 reg_corecfg_rsv0_emi_req_mask_b; + u8 reg_corecfg_rsv0_infra_req_mask_b; + u8 reg_corecfg_rsv0_pmic_req_mask_b; + u8 reg_corecfg_rsv0_srcclkena_mask_b; + u8 reg_corecfg_rsv0_vcore_req_mask_b; + u8 reg_corecfg_rsv0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_7 */ u8 reg_cpueb_apsrc_req_mask_b; u8 reg_cpueb_ddren_req_mask_b; u8 reg_cpueb_emi_req_mask_b; u8 reg_cpueb_infra_req_mask_b; u8 reg_cpueb_pmic_req_mask_b; u8 reg_cpueb_srcclkena_mask_b; + u8 reg_cpueb_vcore_req_mask_b; u8 reg_cpueb_vrf18_req_mask_b; u8 reg_disp0_apsrc_req_mask_b; u8 reg_disp0_ddren_req_mask_b; @@ -284,8 +329,6 @@ u8 reg_disp0_vrf18_req_mask_b; u8 reg_disp1_apsrc_req_mask_b; u8 reg_disp1_ddren_req_mask_b; - - /* SPM_SRC_MASK_5 */ u8 reg_disp1_emi_req_mask_b; u8 reg_disp1_infra_req_mask_b; u8 reg_disp1_pmic_req_mask_b; @@ -293,12 +336,12 @@ u8 reg_disp1_vrf18_req_mask_b; u8 reg_dpm_apsrc_req_mask_b; u8 reg_dpm_ddren_req_mask_b; + + /* SPM_SRC_MASK_8 */ u8 reg_dpm_emi_req_mask_b; u8 reg_dpm_infra_req_mask_b; u8 reg_dpm_pmic_req_mask_b; u8 reg_dpm_srcclkena_mask_b; - - /* SPM_SRC_MASK_6 */ u8 reg_dpm_vcore_req_mask_b; u8 reg_dpm_vrf18_req_mask_b; u8 reg_dpmaif_apsrc_req_mask_b; @@ -307,17 +350,26 @@ u8 reg_dpmaif_infra_req_mask_b; u8 reg_dpmaif_pmic_req_mask_b; u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_vcore_req_mask_b; u8 reg_dpmaif_vrf18_req_mask_b; + + /* SPM_SRC_MASK_9 */ u8 reg_dvfsrc_level_req_mask_b; u8 reg_emisys_apsrc_req_mask_b; u8 reg_emisys_ddren_req_mask_b; u8 reg_emisys_emi_req_mask_b; + u8 reg_emisys_infra_req_mask_b; + u8 reg_emisys_pmic_req_mask_b; + u8 reg_emisys_srcclkena_mask_b; + u8 reg_emisys_vcore_req_mask_b; + u8 reg_emisys_vrf18_req_mask_b; u8 reg_gce_apsrc_req_mask_b; u8 reg_gce_ddren_req_mask_b; u8 reg_gce_emi_req_mask_b; u8 reg_gce_infra_req_mask_b; u8 reg_gce_pmic_req_mask_b; u8 reg_gce_srcclkena_mask_b; + u8 reg_gce_vcore_req_mask_b; u8 reg_gce_vrf18_req_mask_b; u8 reg_gpueb_apsrc_req_mask_b; u8 reg_gpueb_ddren_req_mask_b; @@ -325,8 +377,7 @@ u8 reg_gpueb_infra_req_mask_b; u8 reg_gpueb_pmic_req_mask_b; u8 reg_gpueb_srcclkena_mask_b; - - /* SPM_SRC_MASK_7 */ + u8 reg_gpueb_vcore_req_mask_b; u8 reg_gpueb_vrf18_req_mask_b; u8 reg_hwccf_apsrc_req_mask_b; u8 reg_hwccf_ddren_req_mask_b; @@ -335,6 +386,8 @@ u8 reg_hwccf_pmic_req_mask_b; u8 reg_hwccf_srcclkena_mask_b; u8 reg_hwccf_vcore_req_mask_b; + + /* SPM_SRC_MASK_10 */ u8 reg_hwccf_vrf18_req_mask_b; u8 reg_img_apsrc_req_mask_b; u8 reg_img_ddren_req_mask_b; @@ -347,6 +400,9 @@ u8 reg_infrasys_ddren_req_mask_b; u8 reg_infrasys_emi_req_mask_b; u8 reg_infrasys_infra_req_mask_b; + u8 reg_infrasys_pmic_req_mask_b; + u8 reg_infrasys_srcclkena_mask_b; + u8 reg_infrasys_vcore_req_mask_b; u8 reg_infrasys_vrf18_req_mask_b; u8 reg_ipic_infra_req_mask_b; u8 reg_ipic_vrf18_req_mask_b; @@ -356,15 +412,16 @@ u8 reg_mcu_infra_req_mask_b; u8 reg_mcu_pmic_req_mask_b; u8 reg_mcu_srcclkena_mask_b; + u8 reg_mcu_vcore_req_mask_b; u8 reg_mcu_vrf18_req_mask_b; u8 reg_md_apsrc_req_mask_b; u8 reg_md_ddren_req_mask_b; - - /* SPM_SRC_MASK_8 */ u8 reg_md_emi_req_mask_b; u8 reg_md_infra_req_mask_b; u8 reg_md_pmic_req_mask_b; u8 reg_md_srcclkena_mask_b; + + /* SPM_SRC_MASK_11 */ u8 reg_md_srcclkena1_mask_b; u8 reg_md_vcore_req_mask_b; u8 reg_md_vrf18_req_mask_b; @@ -374,6 +431,7 @@ u8 reg_mm_proc_infra_req_mask_b; u8 reg_mm_proc_pmic_req_mask_b; u8 reg_mm_proc_srcclkena_mask_b; + u8 reg_mm_proc_vcore_req_mask_b; u8 reg_mm_proc_vrf18_req_mask_b; u8 reg_mml0_apsrc_req_mask_b; u8 reg_mml0_ddren_req_mask_b; @@ -393,11 +451,11 @@ u8 reg_ovl0_ddren_req_mask_b; u8 reg_ovl0_emi_req_mask_b; u8 reg_ovl0_infra_req_mask_b; - - /* SPM_SRC_MASK_9 */ u8 reg_ovl0_pmic_req_mask_b; u8 reg_ovl0_srcclkena_mask_b; u8 reg_ovl0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_12 */ u8 reg_ovl1_apsrc_req_mask_b; u8 reg_ovl1_ddren_req_mask_b; u8 reg_ovl1_emi_req_mask_b; @@ -413,13 +471,32 @@ u8 reg_pcie0_srcclkena_mask_b; u8 reg_pcie0_vcore_req_mask_b; u8 reg_pcie0_vrf18_req_mask_b; + u8 reg_pcie1_apsrc_req_mask_b; + u8 reg_pcie1_ddren_req_mask_b; + u8 reg_pcie1_emi_req_mask_b; + u8 reg_pcie1_infra_req_mask_b; + u8 reg_pcie1_pmic_req_mask_b; + u8 reg_pcie1_srcclkena_mask_b; + u8 reg_pcie1_vcore_req_mask_b; + u8 reg_pcie1_vrf18_req_mask_b; u8 reg_perisys_apsrc_req_mask_b; u8 reg_perisys_ddren_req_mask_b; u8 reg_perisys_emi_req_mask_b; u8 reg_perisys_infra_req_mask_b; u8 reg_perisys_pmic_req_mask_b; u8 reg_perisys_srcclkena_mask_b; + u8 reg_perisys_vcore_req_mask_b; u8 reg_perisys_vrf18_req_mask_b; + u8 reg_pmsr_apsrc_req_mask_b; + + /* SPM_SRC_MASK_13 */ + u8 reg_pmsr_ddren_req_mask_b; + u8 reg_pmsr_emi_req_mask_b; + u8 reg_pmsr_infra_req_mask_b; + u8 reg_pmsr_pmic_req_mask_b; + u8 reg_pmsr_srcclkena_mask_b; + u8 reg_pmsr_vcore_req_mask_b; + u8 reg_pmsr_vrf18_req_mask_b; u8 reg_scp_apsrc_req_mask_b; u8 reg_scp_ddren_req_mask_b; u8 reg_scp_emi_req_mask_b; @@ -427,8 +504,6 @@ u8 reg_scp_pmic_req_mask_b; u8 reg_scp_srcclkena_mask_b; u8 reg_scp_vcore_req_mask_b; - - /* SPM_SRC_MASK_10 */ u8 reg_scp_vrf18_req_mask_b; u8 reg_spu_hwrot_apsrc_req_mask_b; u8 reg_spu_hwrot_ddren_req_mask_b; @@ -436,6 +511,7 @@ u8 reg_spu_hwrot_infra_req_mask_b; u8 reg_spu_hwrot_pmic_req_mask_b; u8 reg_spu_hwrot_srcclkena_mask_b; + u8 reg_spu_hwrot_vcore_req_mask_b; u8 reg_spu_hwrot_vrf18_req_mask_b; u8 reg_spu_ise_apsrc_req_mask_b; u8 reg_spu_ise_ddren_req_mask_b; @@ -443,10 +519,14 @@ u8 reg_spu_ise_infra_req_mask_b; u8 reg_spu_ise_pmic_req_mask_b; u8 reg_spu_ise_srcclkena_mask_b; + u8 reg_spu_ise_vcore_req_mask_b; u8 reg_spu_ise_vrf18_req_mask_b; + + /* SPM_SRC_MASK_14 */ u8 reg_srcclkeni_infra_req_mask_b; u8 reg_srcclkeni_pmic_req_mask_b; u8 reg_srcclkeni_srcclkena_mask_b; + u8 reg_srcclkeni_vcore_req_mask_b; u8 reg_sspm_apsrc_req_mask_b; u8 reg_sspm_ddren_req_mask_b; u8 reg_sspm_emi_req_mask_b; @@ -458,12 +538,21 @@ u8 reg_ssrsys_ddren_req_mask_b; u8 reg_ssrsys_emi_req_mask_b; u8 reg_ssrsys_infra_req_mask_b; - - /* SPM_SRC_MASK_11 */ u8 reg_ssrsys_pmic_req_mask_b; u8 reg_ssrsys_srcclkena_mask_b; + u8 reg_ssrsys_vcore_req_mask_b; u8 reg_ssrsys_vrf18_req_mask_b; + u8 reg_ssusb_apsrc_req_mask_b; + u8 reg_ssusb_ddren_req_mask_b; + u8 reg_ssusb_emi_req_mask_b; + u8 reg_ssusb_infra_req_mask_b; + u8 reg_ssusb_pmic_req_mask_b; + u8 reg_ssusb_srcclkena_mask_b; + u8 reg_ssusb_vcore_req_mask_b; + u8 reg_ssusb_vrf18_req_mask_b; u8 reg_uart_hub_infra_req_mask_b; + + /* SPM_SRC_MASK_15 */ u8 reg_uart_hub_pmic_req_mask_b; u8 reg_uart_hub_srcclkena_mask_b; u8 reg_uart_hub_vcore_req_mask_b; @@ -474,6 +563,7 @@ u8 reg_ufs_infra_req_mask_b; u8 reg_ufs_pmic_req_mask_b; u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_vcore_req_mask_b; u8 reg_ufs_vrf18_req_mask_b; u8 reg_vdec_apsrc_req_mask_b; u8 reg_vdec_ddren_req_mask_b; @@ -489,11 +579,36 @@ u8 reg_venc_pmic_req_mask_b; u8 reg_venc_srcclkena_mask_b; u8 reg_venc_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv0_ddren_req_mask_b; + u8 reg_vlpcfg_rsv0_emi_req_mask_b; + u8 reg_vlpcfg_rsv0_infra_req_mask_b; + u8 reg_vlpcfg_rsv0_pmic_req_mask_b; + u8 reg_vlpcfg_rsv0_srcclkena_mask_b; + + /* SPM_SRC_MASK_16 */ + u8 reg_vlpcfg_rsv0_vcore_req_mask_b; + u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv1_ddren_req_mask_b; + u8 reg_vlpcfg_rsv1_emi_req_mask_b; + u8 reg_vlpcfg_rsv1_infra_req_mask_b; + u8 reg_vlpcfg_rsv1_pmic_req_mask_b; + u8 reg_vlpcfg_rsv1_srcclkena_mask_b; + u8 reg_vlpcfg_rsv1_vcore_req_mask_b; + u8 reg_vlpcfg_rsv1_vrf18_req_mask_b;
/* SPM_EVENT_CON_MISC */ u8 reg_srcclken_fast_resp; u8 reg_csyspwrup_ack_mask;
+ /* SPM_SRC_MASK_17 */ + u32 reg_spm_sw_rsv_vcore_req_mask_b; + u32 reg_spm_sw_rsv_pmic_req_mask_b; + + /* SPM_SRC_MASK_18 */ + u32 reg_spm_sw_rsv_srcclkena_mask_b; + /* SPM_WAKEUP_EVENT_MASK */ u32 reg_wakeup_event_mask;
@@ -546,7 +661,15 @@ u8 reserved10[40]; u32 md32pcm_sta; u32 md32pcm_pc; - u8 reserved11[104]; + u32 spm_ulposc_en_cg_con; + u32 spm_resource_ulposc_ack_con; + u32 spm_ulposc_off_mode_con; + u32 spm_ulposc_ack_sta; + u32 spm_reosource_ulposc_mask; + u32 spm_req_block; + u32 dvfs_ips_ctrl; + u32 top_cksys_con; + u8 reserved11[72]; u32 spm_ap_standby_con; u32 cpu_wfi_en; u32 cpu_wfi_en_set; @@ -567,16 +690,17 @@ u32 spm_cputop_pwr_con; u32 spm_cpu_pwr_con[8]; u32 spm_mcupm_spmc_con; - u8 reserved13[20]; + u32 sodi5_mcusys_con; + u8 reserved13[16]; u32 spm_dpm_p2p_sta; u32 spm_dpm_p2p_con; u32 spm_dpm_intf_sta; u32 spm_dpm_wb_con; - u32 pcm_apwdt_latch[20]; + u8 reserved14[80]; u32 spm_pwrap_con; u32 spm_pwrap_con_sta; u32 spm_pmic_spmi_con; - u8 reserved14[4]; + u8 reserved15[4]; u32 spm_pwrap_cmd[32]; u32 dvfsrc_event_sta; u32 spm_force_dvfs; @@ -588,13 +712,23 @@ u32 spm_dvfs_con; u32 spm_sramrc_con; u32 spm_srclkenrc_con; - u32 spm_dpsw_con; + u8 reserved16[4]; u32 spm_dpsw_vapu_iso_con; u32 spm_dpsw_vmm_iso_con; u32 spm_dpsw_vmd_iso_con; u32 spm_dpsw_vmodem_iso_con; u32 spm_dpsw_vcore_iso_con; - u8 reserved15[48]; + u32 spm_dpsw_con; + u32 spm_dpsw_con_set; + u32 spm_dpsw_con_clr; + u32 spm_dpsw_aoc_iso_con; + u32 spm_dpsw_aoc_iso_con_set; + u32 spm_dpsw_aoc_iso_con_clr; + u32 spm_dpsw_force_switch_con; + u32 spm_dpsw_force_switch_con_set; + u32 spm_dpsw_force_switch_con_clr; + u32 spm2dpsw_ctrl_ack; + u8 reserved17[8]; u32 ulposc_con; u32 ap_mdsrc_req; u32 spm2md_switch_ctrl; @@ -612,7 +746,13 @@ u32 cirq_bypass_con; u32 aoc_vcore_sram_con; u32 spm2emi_pdn_ctrl; - u8 reserved16[28]; + u32 vlp_rtff_ctrl_mask; + u32 vlp_rtff_ctrl_mask_set; + u32 vlp_rtff_ctrl_mask_clr; + u32 vlp_rtff_ctrl_mask_2; + u32 vlp_rtff_ctrl_mask_2_set; + u32 vlp_rtff_ctrl_mask_2_clr; + u8 reserved18[4]; u32 reg_module_sw_cg_ddren_req_mask[4]; u32 reg_module_sw_cg_vrf18_req_mask[4]; u32 reg_module_sw_cg_infra_req_mask[4]; @@ -636,7 +776,7 @@ u32 reg_module_busy_f26m_req_mask; u32 reg_module_busy_pmic_req_mask; u32 reg_module_busy_vcore_req_mask; - u8 reserved17[8]; + u8 reserved19[8]; u32 sys_timer_con; u32 sys_timer_value_l; u32 sys_timer_value_h; @@ -651,8 +791,7 @@ u32 spm_counter[3]; u32 pcm_wdt_val; u32 pcm_wdt_out; - u32 pcm_apwdt_latch_20[19]; - u8 reserved18[4]; + u8 reserved20[80]; u32 spm_sw_flag_0; u32 spm_sw_debug_0; u32 spm_sw_flag_1; @@ -662,7 +801,7 @@ u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; u32 spm_bk_pcm_timer; - u8 reserved19[12]; + u8 reserved21[12]; u32 spm_rsv_con_0; u32 spm_rsv_con_1; u32 spm_rsv_sta_0; @@ -680,7 +819,7 @@ u32 spm_sw_debug_2; u32 spm_dv_con_0; u32 spm_dv_con_1; - u8 reserved20[8]; + u8 reserved22[8]; u32 spm_sema_m[8]; u32 spm2adsp_mailbox; u32 adsp2spm_mailbox; @@ -693,7 +832,7 @@ u32 vcore_rtff_ctrl_mask_set; u32 vcore_rtff_ctrl_mask_clr; u32 spm_sram_srclkeno_mask; - u8 reserved21[256]; + u8 reserved23[256]; u32 spm_wakeup_sta; u32 spm_wakeup_ext_sta; u32 spm_wakeup_event_mask; @@ -701,46 +840,32 @@ u32 spm_wakeup_event_sens; u32 spm_wakeup_event_clear; u32 spm_src_req; - u32 spm_src_mask[12]; - u32 spm_req_sta[12]; + u32 spm_src_mask[17]; + u32 spm_req_sta[17]; u32 spm_ipc_wakeup_req; u32 ipc_wakeup_req_mask_sta; u32 spm_event_con_misc; u32 ddren_dbc_con; u32 spm_resource_ack_con[2]; - u32 spm_resource_ack_mask[9]; + u32 spm_resource_ack_mask[13]; u32 spm_event_counter_clear; u32 spm_vcore_event_count_sta; u32 spm_pmic_event_count_sta; - u32 spm_srcclkena_event_count_sta; + u32 spm_srclkena_event_count_sta; u32 spm_infra_event_count_sta; u32 spm_vrf18_event_count_sta; u32 spm_emi_event_count_sta; u32 spm_apsrc_event_count_sta; u32 spm_ddren_event_count_sta; - u32 pcm_wdt_latch[39]; - u32 pcm_wdt_latch_spare[10]; - u32 dramc_gating_err_latch[6]; - u32 dramc_gating_err_latch_spare_0; - u32 spm_debug_con; - u32 spm_ack_chk_con_0; - u32 spm_ack_chk_sel_0; - u32 spm_ack_chk_timer_0; - u32 spm_ack_chk_sta_0; - u32 spm_ack_chk_con_1; - u32 spm_ack_chk_sel_1; - u32 spm_ack_chk_timer_1; - u32 spm_ack_chk_sta_1; - u32 spm_ack_chk_con_2; - u32 spm_ack_chk_sel_2; - u32 spm_ack_chk_timer_2; - u32 spm_ack_chk_sta_2; - u32 spm_ack_chk_con_3; - u32 spm_ack_chk_sel_3; - u32 spm_ack_chk_timer_3; - u32 spm_ack_chk_sta_3; + u32 spm_src_mask_17; + u32 spm_src_mask_18; + u32 spm_resource_ack_mask_13; + u32 spm_resource_ack_mask_14; + u32 spm_req_sta_17; + u32 spm_req_sta_18; + u8 reserved24[212]; u32 md32pcm_cfgreg_sw_rstn; - u8 reserved22[508]; + u8 reserved25[508]; u32 md32pcm_dma0_src; u32 md32pcm_dma0_dst; u32 md32pcm_dma0_wppt; @@ -748,101 +873,75 @@ u32 md32pcm_dma0_count; u32 md32pcm_dma0_con; u32 md32pcm_dma0_start; - u8 reserved23[8]; + u8 reserved26[8]; u32 md32pcm_dma0_rlct; - u8 reserved24[276]; - u32 md32pcm_intc_irq_raw_sta; - u8 reserved25[192]; + u8 reserved27[472]; u32 md1_pwr_con; u32 conn_pwr_con; - u32 ifr_pwr_con; + u32 apifr_io_pwr_con; + u32 apifr_mem_pwr_con; u32 peri_pwr_con; - u32 peri_usb0_pwr_con; + u32 peri_ether_pwr_con; + u32 ssusb_dp_phy_p0_pwr_con; + u32 ssusb_p0_pwr_con; + u32 ssusb_p1_pwr_con; + u32 ssusb_p23_pwr_con; + u32 ssusb_phy_p2_pwr_con; u32 ufs0_pwr_con; u32 ufs0_phy_pwr_con; u32 pextp_mac0_pwr_con; u32 pextp_mac1_pwr_con; + u32 pextp_mac2_pwr_con; u32 pextp_phy0_pwr_con; u32 pextp_phy1_pwr_con; + u32 pextp_phy2_pwr_con; u32 audio_pwr_con; u32 adsp_core1_pwr_con; u32 adsp_top_pwr_con; u32 adsp_infra_pwr_con; u32 adsp_ao_pwr_con; - u32 isp_traw_pwr_con; - u32 isp_dip1_pwr_con; - u32 isp_main_pwr_con; - u32 isp_vcore_pwr_con; - u32 vde0_pwr_con; - u32 vde1_pwr_con; - u32 vde_vcore0_pwr_con; - u32 vde_vcore1_pwr_con; - u32 ven0_pwr_con; - u32 ven1_pwr_con; - u32 ven2_pwr_con; - u32 cam_mraw_pwr_con; - u32 cam_suba_pwr_con; - u32 cam_subb_pwr_con; - u32 cam_subc_pwr_con; - u32 cam_main_pwr_con; - u32 cam_vcore_pwr_con; - u32 cam_ccu_pwr_con; - u32 cam_ccu_ao_pwr_con; - u32 disp_vcore_pwr_con; - u32 mml0_pwr_con; - u32 mml1_pwr_con; - u32 dis0_pwr_con; - u32 dis1_pwr_con; - u32 ovl0_pwr_con; - u32 ovl1_pwr_con; - u32 mm_infra_pwr_con; u32 mm_proc_pwr_con; - u32 dp_tx_pwr_con; u32 scp_pwr_con; - u32 dpyd0_pwr_con; - u32 dpyd1_pwr_con; - u32 dpyd2_pwr_con; - u32 dpyd3_pwr_con; - u32 dpya0_pwr_con; - u32 dpya1_pwr_con; - u32 dpya2_pwr_con; - u32 dpya3_pwr_con; u32 dpm0_pwr_con; u32 dpm1_pwr_con; u32 dpm2_pwr_con; u32 dpm3_pwr_con; u32 emi0_pwr_con; u32 emi1_pwr_con; - u32 cpueb_pwr_con; - u32 csi_rx_pwr_con; + u32 emi_infra_pwr_con; u32 ssrsys_pwr_con; u32 spu_ise_pwr_con; u32 spu_hwrot_pwr_con; + u32 vlp_pwr_con; + u32 hsgmii0_pwr_con; + u32 hsgmii1_pwr_con; + u32 mfg_vlp_pwr_con; + u32 mcusys_busblk_pwr_con; + u32 cpueb_pwr_con; u32 mfg0_pwr_con; - u32 unipro_pdn_sram_con; - u32 ufs_sleep_sram_con; - u32 ccu_sleep_sram_con; - u32 mm_infra_ao_pdn_sram_con; - u32 infra_sleep_sram_con; - u32 peri_sleep_sram_con; - u32 nth_emi_slb_sram_con; - u32 nth_emi_slb_sram_ack; - u32 sth_emi_slb_sram_con; - u32 sth_emi_slb_sram_ack; - u32 ssr_sleep_sram_con; - u32 spu_ise_sleep_sram_con; - u32 spu_hwrot_sleep_sram_con; - u32 infra_hre_sram_con; - u32 emi_hre_sram_con; - u32 mm_hre_sram_con; - u32 mml_hre_sram_con; u32 adsp_hre_sram_con; + u32 ccu_sleep_sram_con; u32 efuse_sram_con; + u32 emi_hre_sram_con; + u32 infra_hre_sram_con; + u32 infra_sleep_sram_con; + u32 mml_hre_sram_con; + u32 mm_hre_sram_con; + u32 mm_infra_ao_pdn_sram_con; + u32 nth_emi_slb_sram_con; + u32 peri_sleep_sram_con; u32 spm_sram_con; + u32 spu_hwrot_sleep_sram_con; + u32 spu_ise_sleep_sram_con; u32 sspm_sram_con; + u32 ssr_sleep_sram_con; + u32 sth_emi_slb_sram_con; + u32 ufs_sleep_sram_con; + u32 unipro_pdn_sram_con; u32 cpu_buck_iso_con; u32 md_buck_iso_con; u32 soc_buck_iso_con; + u32 reserved28[2]; u32 soc_buck_iso_con_set; u32 soc_buck_iso_con_clr; u32 pwr_status; @@ -852,39 +951,194 @@ u32 xpu_pwr_status; u32 xpu_pwr_status_2nd; u32 dfd_soc_pwr_latch; - u8 reserved26[68]; + u32 nth_emi_slb_sram_ack; + u32 sth_emi_slb_sram_ack; + u32 dpyd0_pwr_con; + u32 dpyd1_pwr_con; + u32 dpyd2_pwr_con; + u32 dpyd3_pwr_con; + u32 dpya0_pwr_con; + u32 dpya1_pwr_con; + u32 dpya2_pwr_con; + u32 reserved29[2]; + u32 dpya3_pwr_con; + u32 scp_2_pwr_con; + u32 rsv_0_sleep_sram_con; + u32 rsv_1_sleep_sram_con; + u32 apifr_mem_sleep_sram_con; + u32 rsv_0_pwr_con; + u32 rsv_1_pwr_con; + u32 reserved30[22]; u32 spm_twam_con; u32 spm_twam_window_len; u32 spm_twam_idle_sel; u32 spm_twam_last_sta[4]; u32 spm_twam_curr_sta[4]; u32 spm_twam_timer_out; + u32 reserved31[8192]; + u32 md1_ssyspm_con; + u32 conn_ssyspm_con; + u32 apifr_io_ssyspm_con; + u32 apifr_mem_ssyspm_con; + u32 peri_ssyspm_con; + u32 peri_ether_ssyspm_con; + u32 ssusb_dp_phy_p0_ssyspm_con; + u32 ssusb_p0_ssyspm_con; + u32 ssusb_p1_ssyspm_con; + u32 ssusb_p23_ssyspm_con; + u32 ssusb_phy_p2_ssyspm_con; + u32 ufs0_ssyspm_con; + u32 ufs0_phy_ssyspm_con; + u32 pextp_mac0_ssyspm_con; + u32 pextp_mac1_ssyspm_con; + u32 pextp_mac2_ssyspm_con; + u32 pextp_phy0_ssyspm_con; + u32 pextp_phy1_ssyspm_con; + u32 pextp_phy2_ssyspm_con; + u32 audio_ssyspm_con; + u32 adsp_core1_ssyspm_con; + u32 adsp_top_ssyspm_con; + u32 adsp_infra_ssyspm_con; + u32 adsp_ao_ssyspm_con; + u32 mm_proc_ssyspm_con; + u32 scp_ssyspm_con; + u32 scp_2_ssyspm_con; + u32 dpyd0_ssyspm_con; + u32 dpyd1_ssyspm_con; + u32 dpyd2_ssyspm_con; + u32 dpyd3_ssyspm_con; + u32 dpya0_ssyspm_con; + u32 dpya1_ssyspm_con; + u32 dpya2_ssyspm_con; + u32 dpya3_ssyspm_con; + u32 dpm0_ssyspm_con; + u32 dpm1_ssyspm_con; + u32 dpm2_ssyspm_con; + u32 dpm3_ssyspm_con; + u32 emi0_ssyspm_con; + u32 emi1_ssyspm_con; + u32 emi_infra_ssyspm_con; + u32 ssrsys_ssyspm_con; + u32 spu_ise_ssyspm_con; + u32 spu_hwrot_ssyspm_con; + u32 vlp_ssyspm_con; + u32 hsgmii0_ssyspm_con; + u32 hsgmii1_ssyspm_con; + u32 mfg_vlp_ssyspm_con; + u32 mcusys_busblk_ssyspm_con; + u32 rsv_0_ssyspm_con; + u32 rsv_1_ssyspm_con; + u32 cpueb_ssyspm_con; + u32 mfg0_ssyspm_con; + u32 bus_protect_con; + u32 bus_protect_con_set; + u32 bus_protect_con_clr; + u32 bus_protect_msb_con; + u32 bus_protect_msb_con_set; + u32 bus_protect_msb_con_clr; + u32 bus_protect_cg_con; + u32 bus_protect_cg_con_set; + u32 bus_protect_cg_con_clr; + u32 bus_protect_cg_msb_con; + u32 ocla_en; + u32 ocla_sw_rst; + u32 ocla_config_0; + u32 ocla_cand_mux_sel; + u32 ocla_sleep_sram_con; + u32 ocla_comp_val; + u32 ocla_vcore_req_sel; + u32 ocla_vcore_ack_sel; + u32 ocla_pmic_req_sel; + u32 ocla_pmic_ack_sel; + u32 ocla_26m_req_sel; + u32 ocla_26m_ack_sel; + u32 ocla_infra_req_sel; + u32 ocla_infra_ack_sel; + u32 ocla_buspll_req_sel; + u32 ocla_buspll_ack_sel; + u32 ocla_emi_req_sel; + u32 ocla_emi_ack_sel; + u32 ocla_apsrc_req_sel; + u32 ocla_apsrc_ack_sel; + u32 ocla_ddren_req_sel; + u32 ocla_ddren_ack_sel; + u32 ocla_mtcmos_pwr_on_sel; + u32 ocla_mtcmos_pwr_ack_sel; + u32 ocla_mon_mode[2]; + u32 ocla_bit_seq[2]; + u32 ocla_bit_en; + u32 ocla_timer_lsb; + u32 ocla_timer_msb; + u32 ocla_trig_addr; + u32 ocla_sta; + u32 ocla_level_max_time; + u32 ocla_rsv[6]; + u32 reserved32[24]; + u32 bus_protect_cg_msb_con_set; + u32 bus_protect_cg_msb_con_clr; + u32 bus_protect_rdy; + u32 bus_protect_rdy_msb; + u32 spm_rsv_ulposc_req; + u32 spm_sw_rsv_vcore_req_con; + u32 spm_sw_rsv_vcore_req_con_set; + u32 spm_sw_rsv_vcore_req_con_clr; + u32 spm_lteclksq_bg_off; + u32 reserved33[55]; + u32 pbus_vcore_pkt_ctrl; + u32 pbus_vlp_pkt_ctrl; + u32 reserved34[2]; + u32 pbus_vlp_pkt_data[4]; + u32 pbus_vcore_pkt_data[4]; + u32 pbus_vcore_ctrl; + u32 pbus_vlp_ctrl; + u32 reserved35[2]; + u32 pbus_vcore_rx_pkt_ctrl; + u32 pbus_vlp_rx_pkt_ctrl; + u32 reserved36[2]; + u32 pbus_vlp_rx_pkt_data[4]; + u32 pbus_vcore_rx_pkt_data[4]; + u32 reserved37[100]; + u32 pcm_wdt_latch[39]; + u32 pcm_wdt_latch_spare[10]; + u32 dramc_gating_err_latch[6]; + u32 dramc_gating_err_latch_spare_0; + u32 spm_debug_con; + struct { + u32 con; + u32 sel; + u32 timer; + u32 sta; + } spm_ack_chk[4]; + u32 reserved38[3]; + u32 pcm_apwdt_latch[27]; + u32 reserved39[2]; + u32 pcm_apwdt_latch_27[12]; };
check_member(mtk_spm_regs, spm_wakeup_misc, 0x140); check_member(mtk_spm_regs, spm_mcupm_spmc_con, 0x288); -check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2ac); -check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38c); -check_member(mtk_spm_regs, spm_dpsw_con, 0x3b8); +check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2AC); +check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38C); +check_member(mtk_spm_regs, spm_dpsw_con, 0x3D0); check_member(mtk_spm_regs, spm2emi_pdn_ctrl, 0x440); -check_member(mtk_spm_regs, pcm_wdt_out, 0x5ac); -check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6fc); -check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8bc); -check_member(mtk_spm_regs, spm_ack_chk_sta_3, 0x9fc); -check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); -check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); -check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); -check_member(mtk_spm_regs, soc_buck_iso_con, 0xf64); -check_member(mtk_spm_regs, spm_twam_timer_out, 0xffc); +check_member(mtk_spm_regs, reg_module_busy_vcore_req_mask, 0x4F4); +check_member(mtk_spm_regs, sys_timer_con, 0x500); +check_member(mtk_spm_regs, pcm_wdt_out, 0x5AC); +check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6FC); +check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8F4); +check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00); +check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00); +check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24); +check_member(mtk_spm_regs, md1_pwr_con, 0xE00); +check_member(mtk_spm_regs, soc_buck_iso_con, 0xF00); +check_member(mtk_spm_regs, spm_twam_timer_out, 0xFFC); +check_member(mtk_spm_regs, spm_lteclksq_bg_off, 0x9220); +check_member(mtk_spm_regs, pbus_vcore_pkt_ctrl, 0x9300); +check_member(mtk_spm_regs, pbus_vlp_pkt_data[3], 0x931C); +check_member(mtk_spm_regs, pbus_vcore_rx_pkt_data[3], 0x936C); +check_member(mtk_spm_regs, pcm_wdt_latch, 0x9500); +check_member(mtk_spm_regs, spm_ack_chk[3].sta, 0x9620);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
-static const struct power_domain_data disp[] = { - /* TODO: add disp power domains */ -}; - -static const struct power_domain_data audio[] = { - /* TODO: add audio power domains */ -}; - #endif /* SOC_MEDIATEK_MT8196_SPM_H */ diff --git a/src/soc/mediatek/mt8196/spm.c b/src/soc/mediatek/mt8196/spm.c new file mode 100644 index 0000000..66964fb --- /dev/null +++ b/src/soc/mediatek/mt8196/spm.c @@ -0,0 +1,923 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <delay.h> +#include <soc/mcu_common.h> +#include <soc/pll.h> +#include <soc/spm.h> + +struct mtk_vlpcksys_regs { + u32 reserved0[136]; + u32 vlp_clksq_con1; + u32 reserved1[15]; + u32 vlp_ap_pll_con3; +}; +check_member(mtk_vlpcksys_regs, vlp_clksq_con1, 0x220); +check_member(mtk_vlpcksys_regs, vlp_ap_pll_con3, 0x260); + +struct mtk_vlpdevapc_regs { + u32 vlp_ao_mas_sec_0; + u32 reserved0[319]; + u32 vlp_ao_apc_con; +}; +check_member(mtk_vlpdevapc_regs, vlp_ao_apc_con, 0x500); + +struct mtk_vlpcfg_regs { + u32 reserved0[66]; + u32 debug_mon_reg[2]; +}; +check_member(mtk_vlpcfg_regs, debug_mon_reg[1], 0x10c); + +static struct mtk_vlpcksys_regs *const mtk_vlpcksys = (void *)VLP_CKSYS_BASE; +static struct mtk_vlpdevapc_regs *const mtk_vlpdevapc = (void *)VLP_DEVAPC_BASE; +static struct mtk_vlpcfg_regs *const mtk_vlpcfg = (void *)VLP_CFG_BASE; + +unsigned int mt_spm_version; + +#define SPM_INIT_PCM_FLAG (SPM_FLAG_DISABLE_VCORE_DVS\ + | SPM_FLAG_DISABLE_DDR_DFS\ + | SPM_FLAG_DISABLE_EMI_DFS\ + | SPM_FLAG_DISABLE_BUS_DFS\ + | SPM_FLAG_RUN_COMMON_SCENARIO\ + | SPM_FLAG_ENABLE_MT8196_ES_WA\ + | SPM_FLAG_ENABLE_MT8196_EMI_ES_WA) + +static struct pwr_ctrl spm_init_ctrl = { + /* SPM_SRC_REQ */ + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_apsrc_req = 1, + .reg_spm_ddren_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_emi_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_pmic_req = 0, + .reg_spm_scp_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_vcore_req = 1, + .reg_spm_vrf18_req = 0, + .adsp_mailbox_state = 0, + .apsrc_state = 0, + .ddren_state = 0, + .dvfs_state = 0, + .emi_state = 0, + .f26m_state = 0, + .infra_state = 0, + .pmic_state = 0, + .scp_mailbox_state = 0, + .sspm_mailbox_state = 0, + .sw_mailbox_state = 0, + .vcore_state = 0, + .vrf18_state = 0, + + /* SPM_SRC_MASK_0 */ + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_ddren_req_mask_b = 1, + .reg_apu_emi_req_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_pmic_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_audio_dsp_emi_req_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_pmic_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_vcore_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_cam_apsrc_req_mask_b = 1, + .reg_cam_ddren_req_mask_b = 1, + .reg_cam_emi_req_mask_b = 1, + .reg_cam_infra_req_mask_b = 1, + .reg_cam_pmic_req_mask_b = 1, + .reg_cam_srcclkena_mask_b = 1, + .reg_cam_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_1 */ + .reg_ccif_apsrc_req_mask_b = 0xfff, + .reg_ccif_emi_req_mask_b = 0xfff, + .reg_vlpcfg_rsv0_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv0_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv0_emi_req_mask_b = 1, + .reg_vlpcfg_rsv0_infra_req_mask_b = 1, + .reg_vlpcfg_rsv0_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv0_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv0_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv0_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_2 */ + .reg_ccif_infra_req_mask_b = 0xfff, + .reg_ccif_pmic_req_mask_b = 0xfff, + .reg_vlpcfg_rsv1_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv1_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv1_emi_req_mask_b = 1, + .reg_vlpcfg_rsv1_infra_req_mask_b = 1, + .reg_vlpcfg_rsv1_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv1_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv1_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv1_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_3 */ + .reg_ccif_srcclkena_mask_b = 0xfff, + .reg_ccif_vrf18_req_mask_b = 0xfff, + .reg_ccu_apsrc_req_mask_b = 1, + .reg_ccu_ddren_req_mask_b = 1, + .reg_ccu_emi_req_mask_b = 1, + .reg_ccu_infra_req_mask_b = 1, + .reg_ccu_pmic_req_mask_b = 1, + .reg_ccu_srcclkena_mask_b = 1, + .reg_ccu_vrf18_req_mask_b = 1, + .reg_cg_check_apsrc_req_mask_b = 1, + + /* SPM_SRC_MASK_4 */ + .reg_cg_check_ddren_req_mask_b = 1, + .reg_cg_check_emi_req_mask_b = 1, + .reg_cg_check_infra_req_mask_b = 1, + .reg_cg_check_pmic_req_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 1, + .reg_cg_check_vcore_req_mask_b = 1, + .reg_cg_check_vrf18_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_emi_req_mask_b = 1, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_pmic_req_mask_b = 1, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 1, + .reg_conn_vcore_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_cpueb_apsrc_req_mask_b = 1, + .reg_cpueb_ddren_req_mask_b = 1, + .reg_cpueb_emi_req_mask_b = 1, + .reg_cpueb_infra_req_mask_b = 1, + .reg_cpueb_pmic_req_mask_b = 1, + .reg_cpueb_srcclkena_mask_b = 1, + .reg_cpueb_vrf18_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp0_emi_req_mask_b = 1, + .reg_disp0_infra_req_mask_b = 1, + .reg_disp0_pmic_req_mask_b = 1, + .reg_disp0_srcclkena_mask_b = 1, + .reg_disp0_vrf18_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_5 */ + .reg_disp1_emi_req_mask_b = 1, + .reg_disp1_infra_req_mask_b = 1, + .reg_disp1_pmic_req_mask_b = 1, + .reg_disp1_srcclkena_mask_b = 1, + .reg_disp1_vrf18_req_mask_b = 1, + .reg_dpm_apsrc_req_mask_b = 0xf, + .reg_dpm_ddren_req_mask_b = 0xf, + .reg_dpm_emi_req_mask_b = 0xf, + .reg_dpm_infra_req_mask_b = 0xf, + .reg_dpm_pmic_req_mask_b = 0xf, + .reg_dpm_srcclkena_mask_b = 0xf, + + /* SPM_SRC_MASK_6 */ + .reg_dpm_vcore_req_mask_b = 0xf, + .reg_dpm_vrf18_req_mask_b = 0xf, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + .reg_dpmaif_emi_req_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_pmic_req_mask_b = 1, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dvfsrc_level_req_mask_b = 1, + .reg_emisys_apsrc_req_mask_b = 0, + .reg_emisys_ddren_req_mask_b = 1, + .reg_emisys_emi_req_mask_b = 0, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_gce_emi_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_pmic_req_mask_b = 1, + .reg_gce_srcclkena_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gpueb_apsrc_req_mask_b = 1, + .reg_gpueb_ddren_req_mask_b = 1, + .reg_gpueb_emi_req_mask_b = 1, + .reg_gpueb_infra_req_mask_b = 1, + .reg_gpueb_pmic_req_mask_b = 1, + .reg_gpueb_srcclkena_mask_b = 1, + + /* SPM_SRC_MASK_7 */ + .reg_gpueb_vrf18_req_mask_b = 1, + .reg_hwccf_apsrc_req_mask_b = 1, + .reg_hwccf_ddren_req_mask_b = 1, + .reg_hwccf_emi_req_mask_b = 1, + .reg_hwccf_infra_req_mask_b = 1, + .reg_hwccf_pmic_req_mask_b = 1, + .reg_hwccf_srcclkena_mask_b = 1, + .reg_hwccf_vcore_req_mask_b = 1, + .reg_hwccf_vrf18_req_mask_b = 1, + .reg_img_apsrc_req_mask_b = 1, + .reg_img_ddren_req_mask_b = 1, + .reg_img_emi_req_mask_b = 1, + .reg_img_infra_req_mask_b = 1, + .reg_img_pmic_req_mask_b = 1, + .reg_img_srcclkena_mask_b = 1, + .reg_img_vrf18_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_infrasys_emi_req_mask_b = 0, + .reg_infrasys_infra_req_mask_b = 1, + .reg_infrasys_vrf18_req_mask_b = 1, + .reg_ipic_infra_req_mask_b = 1, + .reg_ipic_vrf18_req_mask_b = 1, + .reg_mcu_apsrc_req_mask_b = 1, + .reg_mcu_ddren_req_mask_b = 1, + .reg_mcu_emi_req_mask_b = 1, + .reg_mcu_infra_req_mask_b = 1, + .reg_mcu_pmic_req_mask_b = 1, + .reg_mcu_srcclkena_mask_b = 1, + .reg_mcu_vrf18_req_mask_b = 1, + .reg_md_apsrc_req_mask_b = 1, + .reg_md_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_8 */ + .reg_md_emi_req_mask_b = 1, + .reg_md_infra_req_mask_b = 1, + .reg_md_pmic_req_mask_b = 1, + .reg_md_srcclkena_mask_b = 1, + .reg_md_srcclkena1_mask_b = 1, + .reg_md_vcore_req_mask_b = 1, + .reg_md_vrf18_req_mask_b = 1, + .reg_mm_proc_apsrc_req_mask_b = 1, + .reg_mm_proc_ddren_req_mask_b = 1, + .reg_mm_proc_emi_req_mask_b = 1, + .reg_mm_proc_infra_req_mask_b = 1, + .reg_mm_proc_pmic_req_mask_b = 1, + .reg_mm_proc_srcclkena_mask_b = 1, + .reg_mm_proc_vrf18_req_mask_b = 1, + .reg_mml0_apsrc_req_mask_b = 1, + .reg_mml0_ddren_req_mask_b = 1, + .reg_mml0_emi_req_mask_b = 1, + .reg_mml0_infra_req_mask_b = 1, + .reg_mml0_pmic_req_mask_b = 1, + .reg_mml0_srcclkena_mask_b = 1, + .reg_mml0_vrf18_req_mask_b = 1, + .reg_mml1_apsrc_req_mask_b = 1, + .reg_mml1_ddren_req_mask_b = 1, + .reg_mml1_emi_req_mask_b = 1, + .reg_mml1_infra_req_mask_b = 1, + .reg_mml1_pmic_req_mask_b = 1, + .reg_mml1_srcclkena_mask_b = 1, + .reg_mml1_vrf18_req_mask_b = 1, + .reg_ovl0_apsrc_req_mask_b = 1, + .reg_ovl0_ddren_req_mask_b = 1, + .reg_ovl0_emi_req_mask_b = 1, + .reg_ovl0_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_9 */ + .reg_ovl0_pmic_req_mask_b = 1, + .reg_ovl0_srcclkena_mask_b = 1, + .reg_ovl0_vrf18_req_mask_b = 1, + .reg_ovl1_apsrc_req_mask_b = 1, + .reg_ovl1_ddren_req_mask_b = 1, + .reg_ovl1_emi_req_mask_b = 1, + .reg_ovl1_infra_req_mask_b = 1, + .reg_ovl1_pmic_req_mask_b = 1, + .reg_ovl1_srcclkena_mask_b = 1, + .reg_ovl1_vrf18_req_mask_b = 1, + .reg_pcie0_apsrc_req_mask_b = 1, + .reg_pcie0_ddren_req_mask_b = 1, + .reg_pcie0_emi_req_mask_b = 1, + .reg_pcie0_infra_req_mask_b = 1, + .reg_pcie0_pmic_req_mask_b = 1, + .reg_pcie0_srcclkena_mask_b = 1, + .reg_pcie0_vcore_req_mask_b = 1, + .reg_pcie0_vrf18_req_mask_b = 1, + .reg_perisys_apsrc_req_mask_b = 1, + .reg_perisys_ddren_req_mask_b = 1, + .reg_perisys_emi_req_mask_b = 1, + .reg_perisys_infra_req_mask_b = 1, + .reg_perisys_pmic_req_mask_b = 1, + .reg_perisys_srcclkena_mask_b = 1, + .reg_perisys_vrf18_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_scp_emi_req_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_pmic_req_mask_b = 1, + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_vcore_req_mask_b = 1, + + /* SPM_SRC_MASK_10 */ + .reg_scp_vrf18_req_mask_b = 1, + .reg_spu_hwrot_apsrc_req_mask_b = 1, + .reg_spu_hwrot_ddren_req_mask_b = 1, + .reg_spu_hwrot_emi_req_mask_b = 1, + .reg_spu_hwrot_infra_req_mask_b = 1, + .reg_spu_hwrot_pmic_req_mask_b = 1, + .reg_spu_hwrot_srcclkena_mask_b = 1, + .reg_spu_hwrot_vrf18_req_mask_b = 1, + .reg_spu_ise_apsrc_req_mask_b = 1, + .reg_spu_ise_ddren_req_mask_b = 1, + .reg_spu_ise_emi_req_mask_b = 1, + .reg_spu_ise_infra_req_mask_b = 1, + .reg_spu_ise_pmic_req_mask_b = 1, + .reg_spu_ise_srcclkena_mask_b = 1, + .reg_spu_ise_vrf18_req_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 3, + .reg_srcclkeni_pmic_req_mask_b = 3, + .reg_srcclkeni_srcclkena_mask_b = 3, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + .reg_sspm_emi_req_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_pmic_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_ssrsys_apsrc_req_mask_b = 1, + .reg_ssrsys_ddren_req_mask_b = 1, + .reg_ssrsys_emi_req_mask_b = 1, + .reg_ssrsys_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_11 */ + .reg_ssrsys_pmic_req_mask_b = 1, + .reg_ssrsys_srcclkena_mask_b = 1, + .reg_ssrsys_vrf18_req_mask_b = 1, + .reg_uart_hub_infra_req_mask_b = 1, + .reg_uart_hub_pmic_req_mask_b = 1, + .reg_uart_hub_srcclkena_mask_b = 1, + .reg_uart_hub_vcore_req_mask_b = 1, + .reg_uart_hub_vrf18_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_ufs_emi_req_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_pmic_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_vdec_apsrc_req_mask_b = 1, + .reg_vdec_ddren_req_mask_b = 1, + .reg_vdec_emi_req_mask_b = 1, + .reg_vdec_infra_req_mask_b = 1, + .reg_vdec_pmic_req_mask_b = 1, + .reg_vdec_srcclkena_mask_b = 1, + .reg_vdec_vrf18_req_mask_b = 1, + .reg_venc_apsrc_req_mask_b = 1, + .reg_venc_ddren_req_mask_b = 1, + .reg_venc_emi_req_mask_b = 1, + .reg_venc_infra_req_mask_b = 1, + .reg_venc_pmic_req_mask_b = 1, + .reg_venc_srcclkena_mask_b = 1, + .reg_venc_vrf18_req_mask_b = 1, + + /* SPM_EVENT_CON_MISC */ + .reg_srcclken_fast_resp = 0, + .reg_csyspwrup_ack_mask = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFF7, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /*sw flag setting */ + .pcm_flags = SPM_INIT_PCM_FLAG, +}; + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 1) | + ((pwrctrl->reg_spm_ddren_req & 0x1) << 2) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | + ((pwrctrl->reg_spm_emi_req & 0x1) << 4) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 5) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 6) | + ((pwrctrl->reg_spm_pmic_req & 0x1) << 7) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_vcore_req & 0x1) << 11) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 12) | + ((pwrctrl->adsp_mailbox_state & 0x1) << 16) | + ((pwrctrl->apsrc_state & 0x1) << 17) | + ((pwrctrl->ddren_state & 0x1) << 18) | + ((pwrctrl->dvfs_state & 0x1) << 19) | + ((pwrctrl->emi_state & 0x1) << 20) | + ((pwrctrl->f26m_state & 0x1) << 21) | + ((pwrctrl->infra_state & 0x1) << 22) | + ((pwrctrl->pmic_state & 0x1) << 23) | + ((pwrctrl->scp_mailbox_state & 0x1) << 24) | + ((pwrctrl->sspm_mailbox_state & 0x1) << 25) | + ((pwrctrl->sw_mailbox_state & 0x1) << 26) | + ((pwrctrl->vcore_state & 0x1) << 27) | + ((pwrctrl->vrf18_state & 0x1) << 28)); + + /* SPM_SRC_MASK_0 */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21)); + + /* SPM_SRC_MASK_1 */ + write32(&mtk_spm->spm_src_mask[1], + ((pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv0_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv0_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv0_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv0_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv0_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv0_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv0_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_2 */ + write32(&mtk_spm->spm_src_mask[2], + ((pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv1_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv1_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv1_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv1_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv1_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv1_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv1_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv1_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_3 */ + write32(&mtk_spm->spm_src_mask[3], + ((pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_4 */ + write32(&mtk_spm->spm_src_mask[4], + ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) | + ((pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_5 */ + write32(&mtk_spm->spm_src_mask[5], + ((pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) | + ((pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) | + ((pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) | + ((pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) | + ((pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) | + ((pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25)); + + /* SPM_SRC_MASK_6 */ + write32(&mtk_spm->spm_src_mask[6], + ((pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) | + ((pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_emi_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_gce_pmic_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_gce_srcclkena_mask_b & 0x1) << 24) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_7 */ + write32(&mtk_spm->spm_src_mask[7], + ((pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_img_emi_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_img_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 14) | + ((pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_infrasys_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_infrasys_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mcu_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mcu_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_mcu_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_mcu_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_8 */ + write32(&mtk_spm->spm_src_mask[8], + ((pwrctrl->reg_md_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_mml0_apsrc_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_mml0_ddren_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_mml0_emi_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mml0_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mml0_pmic_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mml0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mml0_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mml1_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_mml1_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mml1_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mml1_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mml1_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mml1_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mml1_vrf18_req_mask_b & 0x1) << 27) | + (((u32)pwrctrl->reg_ovl0_apsrc_req_mask_b & 0x1) << 28) | + (((u32)pwrctrl->reg_ovl0_ddren_req_mask_b & 0x1) << 29) | + (((u32)pwrctrl->reg_ovl0_emi_req_mask_b & 0x1) << 30) | + (((u32)pwrctrl->reg_ovl0_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_9 */ + write32(&mtk_spm->spm_src_mask[9], + ((pwrctrl->reg_ovl0_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ovl0_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ovl0_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_ovl1_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_ovl1_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_ovl1_emi_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_ovl1_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_ovl1_pmic_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ovl1_srcclkena_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ovl1_vrf18_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_pcie0_emi_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_pcie0_pmic_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 15) | + ((pwrctrl->reg_pcie0_vcore_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 30) | + ((pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_10 */ + write32(&mtk_spm->spm_src_mask[10], + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_spu_hwrot_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_spu_hwrot_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_spu_hwrot_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_spu_hwrot_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_spu_hwrot_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_spu_hwrot_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_spu_hwrot_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_spu_ise_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_spu_ise_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_spu_ise_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_spu_ise_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_spu_ise_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spu_ise_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spu_ise_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 15) | + ((pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 17) | + ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 19) | + ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ssrsys_apsrc_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ssrsys_ddren_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ssrsys_emi_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_ssrsys_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_11 */ + write32(&mtk_spm->spm_src_mask[11], + ((pwrctrl->reg_ssrsys_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ssrsys_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ssrsys_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_uart_hub_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_uart_hub_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_uart_hub_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_uart_hub_vcore_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_uart_hub_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 28)); + + /* SPM_EVENT_CON_MISC */ + write32(&mtk_spm->spm_event_con_misc, + ((pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | + ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + (pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + (pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0); +} + +static void spm_hw_s1_state_monitor(bool en) +{ + if (en) + clrsetbits32(&mtk_spm->spm_ack_chk[3].con, SPM_ACK_CHK_3_CON_CLR_ALL, + SPM_ACK_CHK_3_CON_EN); + else + clrsetbits32(&mtk_spm->spm_ack_chk[3].con, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL, + SPM_ACK_CHK_3_CON_EN); +} + +static void spm_init_ulposc_ctrl(void) +{ + write32(&mtk_spm->spm_reosource_ulposc_mask, 0x0); + + clrbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(16)); + + write32(&mtk_spm->spm_resource_ulposc_ack_con, 0x185); + + setbits32(&mtk_spm->spm_reosource_ulposc_mask, + BIT(2) | BIT(18) | BIT(5) | BIT(21) | BIT(6) | BIT(22) | BIT(1) | BIT(17)); + + setbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(5) | BIT(0) | BIT(16)); + + setbits32(&mtk_spm->spm_rsv_ulposc_req, (0x1)); + + udelay(100); + + write32(&mtk_spm->spm_ulposc_off_mode_con, 0x1); +} + +void spm_register_init(void) +{ + /* Enable scpsys (SPM) clock off control, 0: Topck AO */ + setbits32(&mtk_topckgen->clk_scp_cfg, 0x3FF); + setbits32(&mtk_vlpcksys->vlp_clksq_con1, 0x1); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(1)); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(6)); + + /* Enable register control */ + write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* Init power control register */ + write32(&mtk_spm->spm_power_on_val[1], POWER_ON_VAL1_DEF); + + clrbits32(&mtk_spm->spm_sram_con, 0xF << 16); + + /* SRAM Workaround for Sleep FSM */ + setbits32(&mtk_spm->spm_sram_sleep_ctrl, 0x2 << 8); + + write32(&mtk_spm->spm_power_on_val[1], POWER_ON_VAL1_DEF); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | REG_SSPM_APB_P2P_EN_LSB); + + write32(&mtk_spm->spm_clk_con, (0x10 << 24) | (0x7 << 4)); + + /* clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + setbits32(&mtk_spm->spm_ap_standby_con, BIT(1)); + + write32(&mtk_spm->spm_resource_ack_con[0], 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con[1], 0x00CCCCCC); + + /* Init Other Reg */ + write32(&mtk_spm->spm_ack_chk[3].sel, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk[3].timer, SPM_ACK_CHK_3_HW_S1_CNT); + spm_hw_s1_state_monitor(0); + + /* Init SPM DEBUG Output enable */ + write32(&mtk_spm->spm_debug_con, 0x1); + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con[0], 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con[1], 0x00CCCCCC); + + clrbits32(&mtk_vlpdevapc->vlp_ao_apc_con, BIT(2)); + setbits32(&mtk_vlpdevapc->vlp_ao_mas_sec_0, 0x3); + /* infra sw cg mask for all bit */ + write32p(INFRA_SW_CG, 0xFFFFFFFF); + /* debug_mon for spm pwr_status_msb mtcmos ack check */ + write32(&mtk_vlpcfg->debug_mon_reg[0], (0x79U << 16) | (0x78U << 0)); + write32(&mtk_vlpcfg->debug_mon_reg[1], (0x7BU << 16) | (0x7AU << 0)); + + spm_init_ulposc_ctrl(); + + spm_set_power_control(&spm_init_ctrl); +} + +void spm_reset_and_init_pcm(void) +{ + /* disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* disable pcm timer after leaving FW */ + clrsetbits32(&mtk_spm->pcm_con1, + REG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + clrsetbits32(&mtk_spm->pcm_con1, ~REG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | + REG_SSPM_APB_P2P_EN_LSB); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + u32 val, mask; + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, REG_SPM_EVENT_COUNTER_CLR_LSB); + /* toggle for reset SYS TIMER start point */ + setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_SUSPEND; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrup_ack_mask) + mask &= ~R12_CSYSPWREQ_B; + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, 0); + /* toggle for reset SYS TIMER start point */ + clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); +} + +void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* In the new SOC design, this part has been simplified */ + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +const struct pwr_ctrl *get_pwr_ctrl(void) +{ + return &spm_init_ctrl; +}
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Yidi Lin (Code Review)