Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: [WIP] intel/fsp_baytrail: Fix use of HAVE_SMI_HANDLER ......................................................................
[WIP] intel/fsp_baytrail: Fix use of HAVE_SMI_HANDLER
SCI interrupts need to be programmed regardless?
Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/gpio.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/34255/1
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 8d4e090..2d3d435 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -192,6 +192,9 @@ uint32_t route_reg = 0; int i;
+ if (!CONFIG(HAVE_SMI_HANDLER)) + return; + for (i = 0; i < 8; i++) { /* SMI takes precedence and wake_en implies SCI. */ if (sus[i].smi) { @@ -207,9 +210,7 @@ } }
-#if CONFIG(HAVE_SMI_HANDLER) southcluster_smm_save_gpio_route(route_reg); -#endif }
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: [WIP] intel/fsp_baytrail: Fix use of HAVE_SMI_HANDLER ......................................................................
Patch Set 1: Code-Review+1
Hello Patrick Rudolph, Angel Pons, Huang Jin, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34255
to look at the new patch set (#2).
Change subject: intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER
The code should probably set SCI routing if built with HAVE_SMI_HANDLER=n.
Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_baytrail/gpio.c 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/34255/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/gpio.c:
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... PS2, Line 195: /* FIXME: SCI interrupts should be routed regardlessy. */ Maybe move this check inside lines 201 and 207?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/gpio.c:
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... PS2, Line 195: /* FIXME: SCI interrupts should be routed regardlessy. */
Maybe move this check inside lines 201 and 207?
Change of behaviour, not in the scope of this commit.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/gpio.c:
https://review.coreboot.org/c/coreboot/+/34255/2/src/soc/intel/fsp_baytrail/... PS2, Line 195: /* FIXME: SCI interrupts should be routed regardlessy. */
Change of behaviour, not in the scope of this commit.
Ack
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34255 )
Change subject: intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER ......................................................................
intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLER
The code should probably set SCI routing if built with HAVE_SMI_HANDLER=n.
Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34255 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/fsp_baytrail/gpio.c 1 file changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 8d4e090..2409eaa 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -192,6 +192,10 @@ uint32_t route_reg = 0; int i;
+ /* FIXME: SCI interrupts should be routed regardlessy. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + return; + for (i = 0; i < 8; i++) { /* SMI takes precedence and wake_en implies SCI. */ if (sus[i].smi) { @@ -207,9 +211,7 @@ } }
-#if CONFIG(HAVE_SMI_HANDLER) southcluster_smm_save_gpio_route(route_reg); -#endif }
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)