Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11043
-gerrit
commit ff57c438b9a260fe235a45227e9f2cc06c0d4727 Author: Duncan Laurie dlaurie@chromium.org Date: Wed Jul 22 09:24:23 2015 -0700
skylake: Fix building without serial console
In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default.
Also fix other compile issues when serial console is disabled.
BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled
Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Aaron Durbin adurbin@chromium.org Original-Tested-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/skylake/Kconfig | 2 -- src/soc/intel/skylake/romstage/romstage.c | 3 ++- src/soc/intel/skylake/uart.c | 3 ++- 3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index dbf68a7..d3c541d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -17,8 +17,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION - select CONSOLE_SERIAL8250MEM - select CONSOLE_SERIAL8250MEM_32 select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 919b747..04ffa3e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,7 +50,8 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init();
- pch_uart_init(); + if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32)) + pch_uart_init(); }
/* SOC initialization before RAM is enabled */ diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 03d2ba6..9304118 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -36,7 +36,8 @@ static void pch_uart_read_resources(struct device *dev) pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */ - if (pch_uart_is_debug(dev)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) && + pch_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); res->size = 0x1000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-
Patrick Georgi