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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51397 )
Change subject: soc/intel/alderlake: add processor power limits control support
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Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/51397/comment/d9b974b8_274b591f
PS1, Line 63: Configure turbo power limits 1ms after reset complete bit
I am referring EDS vol-2 (0.8v) Package power MSR register 639 and 641.
639 and 641 are related to reporting the energy status which is updated every 1 ms. Is this done only after RESET_CPL is set (to indicate that all PM relevant configuration) is performed?
But, why do these MSRs matter? I don't think we use these MSRs in set_power_limits().
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